171 	ACCESS_ONCE(ivc->tx_channel->w_count) =  in tegra_ivc_advance_tx()
172 			ACCESS_ONCE(ivc->tx_channel->w_count) + 1;  in tegra_ivc_advance_tx()
192 	if (ivc->tx_channel->state != ivc_state_established)  in tegra_ivc_check_read()
213 	if (ivc->tx_channel->state != ivc_state_established)  in tegra_ivc_check_write()
216 	if (!tegra_ivc_channel_full(ivc, ivc->tx_channel))  in tegra_ivc_check_write()
220 	tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_check_write()
221 	return tegra_ivc_channel_full(ivc, ivc->tx_channel) ? -ENOMEM : 0;  in tegra_ivc_check_write()
293 	*frame = tegra_ivc_frame_pointer(ivc, ivc->tx_channel, ivc->w_pos);  in tegra_ivc_write_get_next_frame()
307 	tegra_ivc_flush_frame(ivc, ivc->tx_channel, ivc->w_pos);  in tegra_ivc_write_advance()
316 	tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_write_advance()
324 	tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_write_advance()
326 	if (tegra_ivc_channel_avail_count(ivc, ivc->tx_channel) == 1)  in tegra_ivc_write_advance()
373 		ivc->tx_channel->w_count = 0;  in tegra_ivc_channel_notified()
389 		ivc->tx_channel->state = ivc_state_ack;  in tegra_ivc_channel_notified()
391 		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_channel_notified()
397 	} else if (ivc->tx_channel->state == ivc_state_sync &&  in tegra_ivc_channel_notified()
410 		ivc->tx_channel->w_count = 0;  in tegra_ivc_channel_notified()
427 		ivc->tx_channel->state = ivc_state_established;  in tegra_ivc_channel_notified()
429 		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_channel_notified()
435 	} else if (ivc->tx_channel->state == ivc_state_ack) {  in tegra_ivc_channel_notified()
449 		ivc->tx_channel->state = ivc_state_established;  in tegra_ivc_channel_notified()
451 		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_channel_notified()
466 	if (ivc->tx_channel->state != ivc_state_established)  in tegra_ivc_channel_notified()
476 	ivc->tx_channel->state = ivc_state_sync;  in tegra_ivc_channel_reset()
478 	tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_channel_reset()
544 	ivc->tx_channel = (struct tegra_ivc_channel_header *)tx_base;  in tegra_ivc_init()