arm/mach-tegra/clock.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/timer.h>
66 	reg = readl(&clkrst->crc_osc_ctrl);
81 	return &clkrst->crc_pll[clkid];
100 		return -1;
101 	data = readl(&pll->pll_base);
102 	*divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
103 	*divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
104 	*divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
105 	data = readl(&pll->pll_misc);
107 	*cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
108 	*lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
133 	 * values for all of the PLLs used in U-Boot, with any
139 		misc_data = readl(&pll->pll_misc);
141 		misc_data = readl(&simple_pll->pll_misc);
142 	misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
143 	misc_data |= cpcon << pllinfo->kcp_shift;
144 	misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
145 	misc_data |= lfcon << pllinfo->kvco_shift;
147 	data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
148 	data |= divp << pllinfo->p_shift;
152 		writel(misc_data, &pll->pll_misc);
153 		writel(data, &pll->pll_base);
155 		writel(misc_data, &simple_pll->pll_misc);
156 		writel(data, &simple_pll->pll_base);
202 		return -1;
227 		return -1;
251 	divider += rate - 1;
254 	if ((s64)divider - 2 < 0)
257 	if ((s64)divider - 2 >= max_divider)
258 		return -1;
260 	return divider - 2;
269 		return -1;
272 		return -1;
277 		return -1;
285 	clrsetbits_le32(&pll->pll_out[pllout >> 1],
330 		 * get_rate_from_divider() would probably require remove the -2
345 			div -= 2;
357  * required child clock rate. This function assumes that a second-stage
363  * @param extra_div	value for the second-stage divisor (not set if this
364  *			function returns -1.
365  * @return divider which should be used, or -1 if nothing is valid
372 	int best_divider = -1;
382 		int error = rate - effective_rate;
385 		if (divider != -1 && error < best_error) {
392 	/* return what we found - *extra_div will already be set */
400  * @param source	Source number (0-3 or 0-7)
403  * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
417 		return -1;
458 		return -1U;
522 		writel(mask, &clkrst->crc_cpu_cmplx_set);
524 		writel(mask, &clkrst->crc_cpu_cmplx_clr);
549 	base = readl(&pll->pll_base);
551 	rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
552 	divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
562 	 * U-Boot at the time of writing this comment.
566 		divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
585  * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
596 	base_reg = readl(&pll->pll_base);
599 	base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
600 	base_reg |= m << pllinfo->m_shift;
602 	base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
603 	base_reg |= n << pllinfo->n_shift;
605 	base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
606 	base_reg |= p << pllinfo->p_shift;
615 			if (base_reg != readl(&pll->pll_base))
617 			return pllp_valid ? 1 : -1;
623 	writel(base_reg, &pll->pll_base);
626 	misc_reg = readl(&pll->pll_misc);
627 	misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
628 	misc_reg |= cpcon << pllinfo->kcp_shift;
629 	writel(misc_reg, &pll->pll_misc);
633 	writel(base_reg, &pll->pll_base);
637 	writel(base_reg, &pll->pll_base);
652 	/* De-assert reset to UART */
665 		return -1;
675 	u32 reg = readl(&pll->pll_base);
679 		return -1;
708 	for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
733 	writel(val, &clkrst->crc_sclk_brst_pol);
740  * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
793 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
799 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
804 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
810 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
820 		setbits_le32(&pmc->pmc_clk_out_cntrl,
821 			     1 << (2 + (clk_id - 1) * 8));
824 		return -EINVAL;