Lines Matching +full:0 +full:x01c68000
39 #define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C)
40 #define SUN4I_SPI0_CTL (0x01C05000 + 0x08)
41 #define SUN4I_SPI0_RX (0x01C05000 + 0x00)
42 #define SUN4I_SPI0_TX (0x01C05000 + 0x04)
43 #define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28)
44 #define SUN4I_SPI0_BC (0x01C05000 + 0x20)
45 #define SUN4I_SPI0_TC (0x01C05000 + 0x24)
47 #define SUN4I_CTL_ENABLE BIT(0)
57 #define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
58 #define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
59 #define SUN6I_SPI0_TCR (0x01C68000 + 0x08)
60 #define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C)
61 #define SUN6I_SPI0_MBC (0x01C68000 + 0x30)
62 #define SUN6I_SPI0_MTC (0x01C68000 + 0x34)
63 #define SUN6I_SPI0_BCC (0x01C68000 + 0x38)
64 #define SUN6I_SPI0_TXD (0x01C68000 + 0x200)
65 #define SUN6I_SPI0_RXD (0x01C68000 + 0x300)
67 #define SUN6I_CTL_ENABLE BIT(0)
74 #define CCM_AHB_GATING0 (0x01C20000 + 0x60)
75 #define CCM_SPI0_CLK (0x01C20000 + 0xA0)
76 #define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
81 #define SPI0_CLK_DIV_BY_2 0x1000
82 #define SPI0_CLK_DIV_BY_4 0x1001
94 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) in spi0_pinmux_setup()
150 writel(0, CCM_SPI0_CLK); in spi0_disable_clock()
203 writeb(0x03, spi_tx_reg); in sunxi_spi0_read_data()
212 while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize) in sunxi_spi0_read_data()
219 while (bufsize-- > 0) in sunxi_spi0_read_data()
231 while (len > 0) { in spi0_read_data()
255 0); in spi0_read_data()
277 int ret = 0; in spl_spi_load_image()
283 spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); in spl_spi_load_image()
310 /* Use priorty 0 to override the default if it happens to be linked in */
311 SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);