358 	struct sunxi_mctl_phy_reg *mctl_phy;  in mctl_channel_init()  local
453 		mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;  in mctl_channel_init()
456 		mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;  in mctl_channel_init()
626 	       &mctl_phy->dcr);  in mctl_channel_init()
630 		clrbits_le32(&mctl_phy->dsgcr, (3 << 6));  in mctl_channel_init()
632 	writel(mr[0], &mctl_phy->mr0);  in mctl_channel_init()
633 	writel(mr[1], &mctl_phy->mr1);  in mctl_channel_init()
634 	writel(mr[2], &mctl_phy->mr2);  in mctl_channel_init()
635 	writel(mr[3], &mctl_phy->mr3);  in mctl_channel_init()
643 		&mctl_phy->dtpr[0]);  in mctl_channel_init()
646 	       &mctl_phy->dtpr[1]);  in mctl_channel_init()
651 	       &mctl_phy->dtpr[2]);  in mctl_channel_init()
661 	writel(0x42C21590, &mctl_phy->ptr[0]);  in mctl_channel_init()
662 	writel(0xD05612C0, &mctl_phy->ptr[1]);  in mctl_channel_init()
670 		writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]);  in mctl_channel_init()
671 		writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]);  in mctl_channel_init()
680 		writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]);  in mctl_channel_init()
681 		writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]);  in mctl_channel_init()
685 	writel(0x00203131, &mctl_phy->acmdlr);  in mctl_channel_init()
689 	       &mctl_phy->dtcr);  in mctl_channel_init()
692 	debug("DX2GCR0 reset: 0x%x\n", readl(&mctl_phy->dx[2].gcr[0]));  in mctl_channel_init()
693 	writel(0x7C000285, &mctl_phy->dx[2].gcr[0]);  in mctl_channel_init()
694 	writel(0x7C000285, &mctl_phy->dx[3].gcr[0]);  in mctl_channel_init()
696 	clrsetbits_le32(&mctl_phy->zq[0].pr, 0xff,  in mctl_channel_init()
698 	clrsetbits_le32(&mctl_phy->zq[1].pr, 0xff,  in mctl_channel_init()
700 	clrsetbits_le32(&mctl_phy->zq[2].pr, 0xff,  in mctl_channel_init()
707 			clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff);  in mctl_channel_init()
708 			clrbits_le32(&mctl_phy->dx[lane].gcr[3],  in mctl_channel_init()
715 			clrsetbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff,  in mctl_channel_init()
718 				setbits_le32(&mctl_phy->dx[lane].gcr[3],  in mctl_channel_init()
721 				setbits_le32(&mctl_phy->dx[lane].gcr[3],  in mctl_channel_init()
726 	writel(0x04058D02, &mctl_phy->zq[0].cr); /* CK/CA */  in mctl_channel_init()
727 	writel(0x04058D02, &mctl_phy->zq[1].cr); /* DX0/DX1 */  in mctl_channel_init()
728 	writel(0x04058D02, &mctl_phy->zq[2].cr); /* DX2/DX3 */  in mctl_channel_init()
733 	setbits_le32(&mctl_phy->dsgcr, 0xf << 24); /* unclear what this is... */  in mctl_channel_init()
735 	clrsetbits_le32(&mctl_phy->pgcr[1],  in mctl_channel_init()
739 	setbits_le32(&mctl_phy->pllcr, 0x3 << 19); /* PLL frequency select */  in mctl_channel_init()
741 	setbits_le32(&mctl_phy->pllcr,  in mctl_channel_init()
746 	clrbits_le32(&mctl_phy->pgcr[0], 0x3f);  in mctl_channel_init()
750 		clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x20df3);  in mctl_channel_init()
752 		clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x2c573);  in mctl_channel_init()
757 	while ((readl(&mctl_phy->pir) & MCTL_PIR_INIT) != MCTL_PIR_INIT) {  in mctl_channel_init()
792 	if (readl(&mctl_phy->pgsr[0]) & MCTL_PGSR0_ERRORS) {  in mctl_channel_init()
810 	clrbits_le32(&mctl_phy->pgcr[3], (1 << 25));  in mctl_channel_init()