Lines Matching refs:CWL
90 u32 CWL; member
361 u32 CWL = 0; in mctl_channel_init() local
438 CWL = para->cl_cwl_table[i].CWL; in mctl_channel_init()
440 debug("found CL/CWL: CL = %d, CWL = %d\n", CL, CWL); in mctl_channel_init()
445 if ((CL == 0) && (CWL == 0)) { in mctl_channel_init()
463 mr[2] = DDR3_MR2_TWL(CWL); in mctl_channel_init()
518 #define WR2PRE (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
520 #define WR2RD (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
525 #define RD2WR (CL + MCTL_BL/2 + 2 - CWL) in mctl_channel_init()
539 writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) | in mctl_channel_init()
574 (1 << 8) | ((MCTL_DIV2(CWL) - 2) << 0), in mctl_channel_init()
860 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
861 { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 }, in sunxi_dram_init()
862 { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 }, in sunxi_dram_init()
863 { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 }, in sunxi_dram_init()
864 { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 } in sunxi_dram_init()