Lines Matching refs:mctl_phy
53 struct sunxi_mctl_phy_reg *mctl_phy; in mctl_dll_init() local
56 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_dll_init()
58 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; in mctl_dll_init()
61 writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr); in mctl_dll_init()
62 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr); in mctl_dll_init()
63 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr); in mctl_dll_init()
65 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr); in mctl_dll_init()
66 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr); in mctl_dll_init()
71 writel(0, &mctl_phy->acdllcr); in mctl_dll_init()
72 writel(0, &mctl_phy->dx0dllcr); in mctl_dll_init()
73 writel(0, &mctl_phy->dx1dllcr); in mctl_dll_init()
75 writel(0, &mctl_phy->dx2dllcr); in mctl_dll_init()
76 writel(0, &mctl_phy->dx3dllcr); in mctl_dll_init()
81 writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr); in mctl_dll_init()
82 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr); in mctl_dll_init()
83 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr); in mctl_dll_init()
85 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr); in mctl_dll_init()
86 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr); in mctl_dll_init()
107 struct sunxi_mctl_phy_reg *mctl_phy; in mctl_channel_init() local
111 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_channel_init()
114 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; in mctl_channel_init()
121 writel(MCTL_PGCR, &mctl_phy->pgcr); in mctl_channel_init()
122 writel(MCTL_MR0, &mctl_phy->mr0); in mctl_channel_init()
123 writel(MCTL_MR1, &mctl_phy->mr1); in mctl_channel_init()
124 writel(MCTL_MR2, &mctl_phy->mr2); in mctl_channel_init()
125 writel(MCTL_MR3, &mctl_phy->mr3); in mctl_channel_init()
128 &mctl_phy->ptr0); in mctl_channel_init()
130 writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); in mctl_channel_init()
131 writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); in mctl_channel_init()
136 &mctl_phy->dtpr0); in mctl_channel_init()
141 (MCTL_TAOND << 0), &mctl_phy->dtpr1); in mctl_channel_init()
144 (MCTL_TEXSR << 0), &mctl_phy->dtpr2); in mctl_channel_init()
147 writel(MCTL_DCR_DDR3, &mctl_phy->dcr); in mctl_channel_init()
148 writel(MCTL_DSGCR, &mctl_phy->dsgcr); in mctl_channel_init()
149 writel(MCTL_DXCCR, &mctl_phy->dxccr); in mctl_channel_init()
150 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr); in mctl_channel_init()
151 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr); in mctl_channel_init()
152 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr); in mctl_channel_init()
153 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr); in mctl_channel_init()
155 mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03); in mctl_channel_init()
157 writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1); in mctl_channel_init()
159 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
160 writel(MCTL_PIR_STEP1, &mctl_phy->pir); in mctl_channel_init()
162 mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f); in mctl_channel_init()
165 if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) { in mctl_channel_init()
167 clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK); in mctl_channel_init()
174 if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) { in mctl_channel_init()
181 if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) { in mctl_channel_init()
184 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); in mctl_channel_init()
185 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); in mctl_channel_init()
186 clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN); in mctl_channel_init()
187 clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN); in mctl_channel_init()
190 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
191 writel(MCTL_PIR_STEP2, &mctl_phy->pir); in mctl_channel_init()
193 mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11); in mctl_channel_init()
195 if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK) in mctl_channel_init()