317 	setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);  in mctl_sys_init()
320 	setbits_le32(&ccm->dram_gate_reset, BIT(0));  in mctl_sys_init()
328 	setbits_le32(&ccm->mbus_cfg, MBUS_RESET);  in mctl_sys_init()
329 	setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);  in mctl_sys_init()
330 	setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);  in mctl_sys_init()
428 	setbits_le32(&mctl_com->cr, BIT(31));  in mctl_com_init()
437 		setbits_le32(&mctl_com->cr, BIT(27));  in mctl_com_init()
514 	setbits_le32(&mctl_phy->pgcr[0], BIT(26));  in mctl_bit_delay_set()
535 	setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));  in mctl_channel_init()
536 	setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));  in mctl_channel_init()
538 	setbits_le32(&mctl_ctl->rfshctl3, BIT(0));  in mctl_channel_init()
539 	setbits_le32(&mctl_ctl->dfimisc, BIT(0));  in mctl_channel_init()
540 	setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));  in mctl_channel_init()
560 		setbits_le32(&mctl_phy->dtcr[1], 0x30000);  in mctl_channel_init()
592 	setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);  in mctl_channel_init()
593 	setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);  in mctl_channel_init()
594 	setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);  in mctl_channel_init()
596 	setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);  in mctl_channel_init()
597 	setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);  in mctl_channel_init()
598 	setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);  in mctl_channel_init()
630 	setbits_le32(&mctl_phy->pgcr[6], BIT(0));  in mctl_channel_init()
672 	setbits_le32(&mctl_com->unk_0x014, BIT(31));  in mctl_channel_init()
745 	setbits_le32(0x7010310, BIT(8));  in sunxi_dram_init()