Lines Matching refs:mctl_phy
80 struct sunxi_mctl_phy_reg * const mctl_phy = in mctl_phy_pir_init() local
83 writel(val | BIT(0), &mctl_phy->pir); in mctl_phy_pir_init()
84 mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0)); in mctl_phy_pir_init()
183 struct sunxi_mctl_phy_reg * const mctl_phy = in mctl_set_timing_lpddr3() local
241 memcpy(mctl_phy->mr, mr_lpddr3, sizeof(mr_lpddr3)); in mctl_set_timing_lpddr3()
269 &mctl_phy->dtpr[0]); in mctl_set_timing_lpddr3()
270 writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); in mctl_set_timing_lpddr3()
271 writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); in mctl_set_timing_lpddr3()
273 &mctl_phy->dtpr[3]); in mctl_set_timing_lpddr3()
274 writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]); in mctl_set_timing_lpddr3()
275 writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); in mctl_set_timing_lpddr3()
276 writel(0x0505, &mctl_phy->dtpr[6]); in mctl_set_timing_lpddr3()
284 writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]); in mctl_set_timing_lpddr3()
285 writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]); in mctl_set_timing_lpddr3()
422 struct sunxi_mctl_phy_reg * const mctl_phy = in mctl_com_init() local
451 writel(DCR_LPDDR3 | DCR_DDR8BANK | 0x400, &mctl_phy->dcr); in mctl_com_init()
470 struct sunxi_mctl_phy_reg * const mctl_phy = in mctl_bit_delay_set() local
476 val = readl(&mctl_phy->dx[i].bdlr0); in mctl_bit_delay_set()
479 writel(val, &mctl_phy->dx[i].bdlr0); in mctl_bit_delay_set()
481 val = readl(&mctl_phy->dx[i].bdlr1); in mctl_bit_delay_set()
484 writel(val, &mctl_phy->dx[i].bdlr1); in mctl_bit_delay_set()
486 val = readl(&mctl_phy->dx[i].bdlr2); in mctl_bit_delay_set()
489 writel(val, &mctl_phy->dx[i].bdlr2); in mctl_bit_delay_set()
491 clrbits_le32(&mctl_phy->pgcr[0], BIT(26)); in mctl_bit_delay_set()
494 val = readl(&mctl_phy->dx[i].bdlr3); in mctl_bit_delay_set()
497 writel(val, &mctl_phy->dx[i].bdlr3); in mctl_bit_delay_set()
499 val = readl(&mctl_phy->dx[i].bdlr4); in mctl_bit_delay_set()
502 writel(val, &mctl_phy->dx[i].bdlr4); in mctl_bit_delay_set()
504 val = readl(&mctl_phy->dx[i].bdlr5); in mctl_bit_delay_set()
507 writel(val, &mctl_phy->dx[i].bdlr5); in mctl_bit_delay_set()
509 val = readl(&mctl_phy->dx[i].bdlr6); in mctl_bit_delay_set()
512 writel(val, &mctl_phy->dx[i].bdlr6); in mctl_bit_delay_set()
514 setbits_le32(&mctl_phy->pgcr[0], BIT(26)); in mctl_bit_delay_set()
518 val = readl(&mctl_phy->acbdlr[i]); in mctl_bit_delay_set()
520 writel(val, &mctl_phy->acbdlr[i]); in mctl_bit_delay_set()
530 struct sunxi_mctl_phy_reg * const mctl_phy = in mctl_channel_init() local
541 clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0); in mctl_channel_init()
543 clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800)); in mctl_channel_init()
544 clrbits_le32(&mctl_phy->pgcr[6], BIT(0)); in mctl_channel_init()
545 clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220); in mctl_channel_init()
547 clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060); in mctl_channel_init()
548 clrbits_le32(&mctl_phy->vtcr[1], BIT(1)); in mctl_channel_init()
551 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800); in mctl_channel_init()
553 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555); in mctl_channel_init()
555 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010); in mctl_channel_init()
560 setbits_le32(&mctl_phy->dtcr[1], 0x30000); in mctl_channel_init()
562 clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000); in mctl_channel_init()
564 clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); in mctl_channel_init()
566 writel(0x00010001, &mctl_phy->rankidr); in mctl_channel_init()
567 writel(0x20000, &mctl_phy->odtcr); in mctl_channel_init()
569 writel(0x0, &mctl_phy->rankidr); in mctl_channel_init()
570 writel(0x10000, &mctl_phy->odtcr); in mctl_channel_init()
574 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040); in mctl_channel_init()
588 clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val); in mctl_channel_init()
589 clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff, in mctl_channel_init()
591 clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff); in mctl_channel_init()
592 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff); in mctl_channel_init()
593 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100); in mctl_channel_init()
594 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4); in mctl_channel_init()
595 clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff); in mctl_channel_init()
596 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff); in mctl_channel_init()
597 setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100); in mctl_channel_init()
598 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4); in mctl_channel_init()
601 writel(0x06060606, &mctl_phy->acbdlr[i]); in mctl_channel_init()
611 writel(0x00000909, &mctl_phy->dx[i].gcr[5]); in mctl_channel_init()
618 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val); in mctl_channel_init()
624 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val); in mctl_channel_init()
630 setbits_le32(&mctl_phy->pgcr[6], BIT(0)); in mctl_channel_init()
631 clrbits_le32(&mctl_phy->pgcr[6], 0xfff8); in mctl_channel_init()
633 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); in mctl_channel_init()
636 if (readl(&mctl_phy->pgsr[0]) & 0x400000) in mctl_channel_init()
642 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 && in mctl_channel_init()
643 (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 && in mctl_channel_init()
644 (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 && in mctl_channel_init()
645 (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) { in mctl_channel_init()
656 if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { in mctl_channel_init()
659 debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0])); in mctl_channel_init()
661 debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0])); in mctl_channel_init()
665 clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40); in mctl_channel_init()
666 clrbits_le32(&mctl_phy->pgcr[1], 0x40); in mctl_channel_init()