301 	clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);  in mctl_sys_init()
302 	clrbits_le32(&ccm->dram_gate_reset, BIT(0));  in mctl_sys_init()
305 	clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);  in mctl_sys_init()
306 	clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);  in mctl_sys_init()
435 		clrbits_le32(&mctl_com->cr, BIT(27));  in mctl_com_init()
491 	clrbits_le32(&mctl_phy->pgcr[0], BIT(26));  in mctl_bit_delay_set()
544 	clrbits_le32(&mctl_phy->pgcr[6], BIT(0));  in mctl_channel_init()
548 	clrbits_le32(&mctl_phy->vtcr[1], BIT(1));  in mctl_channel_init()
564 	clrbits_le32(&mctl_phy->dtcr[1], BIT(1));  in mctl_channel_init()
591 	clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);  in mctl_channel_init()
595 	clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);  in mctl_channel_init()
631 	clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);  in mctl_channel_init()
633 		clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);  in mctl_channel_init()
666 	clrbits_le32(&mctl_phy->pgcr[1], 0x40);  in mctl_channel_init()
667 	clrbits_le32(&mctl_ctl->dfimisc, BIT(0));  in mctl_channel_init()
670 	clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));  in mctl_channel_init()
746 	clrbits_le32(0x7010318, 0x3f);  in sunxi_dram_init()