66 	u32 reg_val;  in mctl_ddr3_reset()  local
69 	reg_val = readl(&timer->cpu_cfg);  in mctl_ddr3_reset()
71 	if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=  in mctl_ddr3_reset()
239 	u32 reg_val;  in mctl_setup_dram_clock()  local
246 	reg_val = readl(&ccm->pll5_cfg);  in mctl_setup_dram_clock()
247 	reg_val &= ~CCM_PLL5_CTRL_M_MASK;		/* set M to 0 (x1) */  in mctl_setup_dram_clock()
248 	reg_val &= ~CCM_PLL5_CTRL_K_MASK;		/* set K to 0 (x1) */  in mctl_setup_dram_clock()
249 	reg_val &= ~CCM_PLL5_CTRL_N_MASK;		/* set N to 0 (x0) */  in mctl_setup_dram_clock()
250 	reg_val &= ~CCM_PLL5_CTRL_P_MASK;		/* set P to 0 (x1) */  in mctl_setup_dram_clock()
253 	reg_val |= CCM_PLL5_CTRL_P(1);  in mctl_setup_dram_clock()
257 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));  in mctl_setup_dram_clock()
258 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));  in mctl_setup_dram_clock()
259 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));  in mctl_setup_dram_clock()
262 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));  in mctl_setup_dram_clock()
263 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));  in mctl_setup_dram_clock()
264 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));  in mctl_setup_dram_clock()
267 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));  in mctl_setup_dram_clock()
268 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));  in mctl_setup_dram_clock()
269 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));  in mctl_setup_dram_clock()
272 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));  in mctl_setup_dram_clock()
273 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));  in mctl_setup_dram_clock()
274 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));  in mctl_setup_dram_clock()
277 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));  in mctl_setup_dram_clock()
278 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));  in mctl_setup_dram_clock()
279 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));  in mctl_setup_dram_clock()
282 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));  in mctl_setup_dram_clock()
283 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));  in mctl_setup_dram_clock()
284 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));  in mctl_setup_dram_clock()
286 	reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN;		/* PLL VCO Gain off */  in mctl_setup_dram_clock()
287 	reg_val |= CCM_PLL5_CTRL_EN;			/* PLL On */  in mctl_setup_dram_clock()
288 	writel(reg_val, &ccm->pll5_cfg);  in mctl_setup_dram_clock()
318 		reg_val = CCM_MBUS_CTRL_GATE |  in mctl_setup_dram_clock()
324 		reg_val = CCM_MBUS_CTRL_GATE |  in mctl_setup_dram_clock()
331 	writel(reg_val, &ccm->mbus_clk_cfg);  in mctl_setup_dram_clock()
387 	u32 reg_val;  in dramc_scan_readpipe()  local
397 	reg_val = readl(&dram->csr);  in dramc_scan_readpipe()
398 	if (reg_val & DRAM_CSR_FAILED)  in dramc_scan_readpipe()
513 	u32 reg_val;  in mctl_set_impedance()  local
543 		reg_val = DRAM_ZQCR0_ZDEN | zdata;  in mctl_set_impedance()
544 		writel(reg_val, &dram->zqcr0);  in mctl_set_impedance()
548 		reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);  in mctl_set_impedance()
549 		writel(reg_val, &dram->zqcr0);  in mctl_set_impedance()
564 	u32 reg_val;  in dramc_init_helper()  local
595 	reg_val = DRAM_DCR_TYPE_DDR3;  in dramc_init_helper()
596 	reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);  in dramc_init_helper()
613 	reg_val |= DRAM_DCR_CHIP_DENSITY(density);  in dramc_init_helper()
614 	reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);  in dramc_init_helper()
615 	reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);  in dramc_init_helper()
616 	reg_val |= DRAM_DCR_CMD_RANK_ALL;  in dramc_init_helper()
617 	reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);  in dramc_init_helper()
618 	writel(reg_val, &dram->dcr);  in dramc_init_helper()
642 	reg_val = DRAM_MR_BURST_LENGTH(0x0);  in dramc_init_helper()
644 	reg_val |= DRAM_MR_POWER_DOWN;  in dramc_init_helper()
646 	reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);  in dramc_init_helper()
647 	reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));  in dramc_init_helper()
648 	writel(reg_val, &dram->mr);  in dramc_init_helper()