1 // SPDX-License-Identifier: GPL-2.0+
7  * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
8  * and earlier U-Boot Allwinner A10 SPL work
10  * (C) Copyright 2007-2012
68 	writel(0, &timer->cpu_cfg);  in mctl_ddr3_reset()
69 	reg_val = readl(&timer->cpu_cfg);  in mctl_ddr3_reset()
73 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
75 		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
79 		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
81 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
83 	/* After the RESET pin is de-asserted, the DDR3 spec requires to wait  in mctl_ddr3_reset()
88 	 * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and  in mctl_ddr3_reset()
90 	 * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to  in mctl_ddr3_reset()
103 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),  in mctl_set_drive()
105 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),  in mctl_set_drive()
115 	clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);  in mctl_itm_disable()
122 	clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);  in mctl_itm_enable()
137 	clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,  in mctl_enable_dll0()
139 	clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);  in mctl_enable_dll0()
142 	clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);  in mctl_enable_dll0()
145 	clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);  in mctl_enable_dll0()
153 	if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==  in mctl_get_number_of_lanes()
171 		clrsetbits_le32(&dram->dllcr[i], 0xf << 14,  in mctl_enable_dllx()
173 		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,  in mctl_enable_dllx()
180 		clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |  in mctl_enable_dllx()
185 		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,  in mctl_enable_dllx()
234 		writel(hpcr_value[i], &dram->hpcr[i]);  in mctl_configure_hostport()
237 static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)  in mctl_setup_dram_clock()  argument
246 	reg_val = readl(&ccm->pll5_cfg);  in mctl_setup_dram_clock()
255 	if (clk >= 540 && clk < 552) {  in mctl_setup_dram_clock()
260 	} else if (clk >= 512 && clk < 528) {  in mctl_setup_dram_clock()
265 	} else if (clk >= 496 && clk < 504) {  in mctl_setup_dram_clock()
270 	} else if (clk >= 468 && clk < 480) {  in mctl_setup_dram_clock()
275 	} else if (clk >= 396 && clk < 408) {  in mctl_setup_dram_clock()
284 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));  in mctl_setup_dram_clock()
288 	writel(reg_val, &ccm->pll5_cfg);  in mctl_setup_dram_clock()
291 	setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);  in mctl_setup_dram_clock()
295 	clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);  in mctl_setup_dram_clock()
296 	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);  in mctl_setup_dram_clock()
298 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);  in mctl_setup_dram_clock()
308 	pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */  in mctl_setup_dram_clock()
331 	writel(reg_val, &ccm->mbus_clk_cfg);  in mctl_setup_dram_clock()
334 	 * open DRAMC AHB & DLL register clock  in mctl_setup_dram_clock()
338 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);  in mctl_setup_dram_clock()
340 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);  in mctl_setup_dram_clock()
346 	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);  in mctl_setup_dram_clock()
348 	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);  in mctl_setup_dram_clock()
355  * in a single 32-bit value using the following format:
356  *   bits [31:26] - DQS gating system latency for byte lane 3
357  *   bits [25:24] - DQS gating phase select for byte lane 3
358  *   bits [23:18] - DQS gating system latency for byte lane 2
359  *   bits [17:16] - DQS gating phase select for byte lane 2
360  *   bits [15:10] - DQS gating system latency for byte lane 1
361  *   bits [ 9:8 ] - DQS gating phase select for byte lane 1
362  *   bits [ 7:2 ] - DQS gating system latency for byte lane 0
363  *   bits [ 1:0 ] - DQS gating phase select for byte lane 0
370 	u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);  in mctl_set_dqs_gating_delay()
372 	u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);  in mctl_set_dqs_gating_delay()
380 	writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);  in mctl_set_dqs_gating_delay()
381 	writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);  in mctl_set_dqs_gating_delay()
390 	clrbits_le32(&dram->csr, DRAM_CSR_FAILED);  in dramc_scan_readpipe()
391 	setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);  in dramc_scan_readpipe()
394 	await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);  in dramc_scan_readpipe()
397 	reg_val = readl(&dram->csr);  in dramc_scan_readpipe()
399 		return -1;  in dramc_scan_readpipe()
410 		setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);  in dramc_clock_output_en()
412 		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);  in dramc_clock_output_en()
417 		setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);  in dramc_clock_output_en()
419 		clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);  in dramc_clock_output_en()
429 static void dramc_set_autorefresh_cycle(u32 clk, u32 density)  in dramc_set_autorefresh_cycle()  argument
434 	tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;  in dramc_set_autorefresh_cycle()
435 	tREFI = (7987 * clk) >> 10;	/* <= 7.8us */  in dramc_set_autorefresh_cycle()
437 	writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);  in dramc_set_autorefresh_cycle()
441 static u32 ddr3_write_recovery(u32 clk)  in ddr3_write_recovery()  argument
444 	u32 twr_ck = (twr_ns * clk + 999) / 1000;  in ddr3_write_recovery()
448 		return twr_ck - 4;  in ddr3_write_recovery()
456  * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
457  * means that DRAM is currently in self-refresh mode and retaining the old
463  * value for this write operation to have any effect. On sun5i hadware this
470 	writel(0x16510000, &dram->ppwrsctl);  in mctl_disable_power_save()
475  * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
485 	 * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to  in mctl_set_cke_delay()
488 	 * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i  in mctl_set_cke_delay()
490 	setbits_le32(&dram->idcr, 0x1ffff);  in mctl_set_cke_delay()
503 	setbits_le32(&dram->ccr, DRAM_CCR_INIT);  in mctl_ddr3_initialize()
504 	await_bits_clear(&dram->ccr, DRAM_CCR_INIT);  in mctl_ddr3_initialize()
518 	 * ZQ calibration is already in progress at this point on sun4i/sun5i  in mctl_set_impedance()
521 	await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);  in mctl_set_impedance()
532 	 * be related to periodic impedance re-calibration. This particular  in mctl_set_impedance()
535 	writel((1 << 24) | (1 << 1), &dram->zqcr1);  in mctl_set_impedance()
538 	/* Needed at least for sun5i, because it does not self clear there */  in mctl_set_impedance()
539 	clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);  in mctl_set_impedance()
544 		writel(reg_val, &dram->zqcr0);  in mctl_set_impedance()
549 		writel(reg_val, &dram->zqcr0);  in mctl_set_impedance()
551 		await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);  in mctl_set_impedance()
554 	/* Needed at least for sun5i, because it does not self clear there */  in mctl_set_impedance()
555 	clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);  in mctl_set_impedance()
558 	writel(DRAM_IOCR_ODT_EN, &dram->iocr);  in mctl_set_impedance()
572 	if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)  in dramc_init_helper()
576 	mctl_setup_dram_clock(para->clock, para->mbus_clock);  in dramc_init_helper()
588 	writel(DRAM_CSEL_MAGIC, &dram->csel);  in dramc_init_helper()
592 	mctl_enable_dll0(para->tpr3);  in dramc_init_helper()
596 	reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);  in dramc_init_helper()
598 	if (para->density == 256)  in dramc_init_helper()
600 	else if (para->density == 512)  in dramc_init_helper()
602 	else if (para->density == 1024)  in dramc_init_helper()
604 	else if (para->density == 2048)  in dramc_init_helper()
606 	else if (para->density == 4096)  in dramc_init_helper()
608 	else if (para->density == 8192)  in dramc_init_helper()
614 	reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);  in dramc_init_helper()
615 	reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);  in dramc_init_helper()
618 	writel(reg_val, &dram->dcr);  in dramc_init_helper()
622 	mctl_set_impedance(para->zq, para->odt_en);  in dramc_init_helper()
630 	await_bits_clear(&dram->ccr, DRAM_CCR_INIT);  in dramc_init_helper()
632 	mctl_enable_dllx(para->tpr3);  in dramc_init_helper()
635 	dramc_set_autorefresh_cycle(para->clock, density);  in dramc_init_helper()
638 	writel(para->tpr0, &dram->tpr0);  in dramc_init_helper()
639 	writel(para->tpr1, &dram->tpr1);  in dramc_init_helper()
640 	writel(para->tpr2, &dram->tpr2);  in dramc_init_helper()
646 	reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);  in dramc_init_helper()
647 	reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));  in dramc_init_helper()
648 	writel(reg_val, &dram->mr);  in dramc_init_helper()
650 	writel(para->emr1, &dram->emr);  in dramc_init_helper()
651 	writel(para->emr2, &dram->emr2);  in dramc_init_helper()
652 	writel(para->emr3, &dram->emr3);  in dramc_init_helper()
655 	clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);  in dramc_init_helper()
659 	if (para->tpr4 & 0x1)  in dramc_init_helper()
660 		setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);  in dramc_init_helper()
675 	if (para->dqs_gating_delay)  in dramc_init_helper()
676 		mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);  in dramc_init_helper()
679 	if (para->active_windowing)  in dramc_init_helper()
680 		clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);  in dramc_init_helper()
682 		setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);  in dramc_init_helper()
701 	if (para->io_width && para->bus_width && para->density)  in dramc_init()
705 	para->io_width  = 16;  in dramc_init()
706 	para->bus_width = 32;  in dramc_init()
708 	/* only A0-A14 address lines on A10/A13, limiting max density to 4096 */  in dramc_init()
709 	para->density = 4096;  in dramc_init()
711 	/* all A0-A15 address lines on A20, which allow density 8192 */  in dramc_init()
712 	para->density = 8192;  in dramc_init()
717 		/* if 32-bit bus width failed, try 16-bit bus width instead */  in dramc_init()
718 		para->bus_width = 16;  in dramc_init()
721 			/* if 16-bit bus width also failed, then bail out */  in dramc_init()
727 	actual_density = (dram_size >> 17) * para->io_width / para->bus_width;  in dramc_init()
729 	if (actual_density != para->density) {  in dramc_init()
730 		/* update the density and re-initialize DRAM again */  in dramc_init()
731 		para->density = actual_density;  in dramc_init()