Lines Matching +full:p +full:- +full:384

1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2012
29 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
30 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
36 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
38 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
42 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
43 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
57 &ccm->apb1_clk_div_cfg); in clock_init_uart()
60 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
61 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1)); in clock_init_uart()
71 setbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
74 clrbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
81 #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ argument
86 (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
113 /* Final catchall entry 384MHz*/
141 axi = axi - 1; in clock_set_pll1()
151 apb0 = apb0 - 1; in clock_set_pll1()
158 &ccm->cpu_ahb_apb0_cfg); in clock_set_pll1()
166 &ccm->cpu_ahb_apb0_cfg); in clock_set_pll1()
169 writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg); in clock_set_pll1()
177 &ccm->cpu_ahb_apb0_cfg); in clock_set_pll1()
188 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); in clock_set_pll3()
194 CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); in clock_set_pll3()
201 uint32_t rval = readl(&ccm->pll3_cfg); in clock_get_pll3()
210 uint32_t rval = readl(&ccm->pll5_cfg); in clock_get_pll5p()
213 int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT); in clock_get_pll5p() local
214 return (24000000 * n * k) >> p; in clock_get_pll5p()
221 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6()