16 /* BSEC REGISTER OFFSET (base relative) */
54  * @base: base address of bsec IP
58 static u32 bsec_check_error(u32 base, u32 otp)  in bsec_check_error()  argument
66 	if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)  in bsec_check_error()
68 	else if (readl(base + BSEC_ERROR_OFF + bank) & bit)  in bsec_check_error()
93  * @base: base address of bsec IP
97 static bool bsec_read_SR_lock(u32 base, u32 otp)  in bsec_read_SR_lock()  argument
99 	return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);  in bsec_read_SR_lock()
104  * @base: base address of bsec IP
108 static bool bsec_read_SP_lock(u32 base, u32 otp)  in bsec_read_SP_lock()  argument
110 	return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);  in bsec_read_SP_lock()
115  * @base: base address of bsec IP
119 static bool bsec_read_SW_lock(u32 base, u32 otp)  in bsec_read_SW_lock()  argument
121 	return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);  in bsec_read_SW_lock()
126  * @base: base address of bsec IP
130 static int bsec_power_safmem(u32 base, bool power)  in bsec_power_safmem()  argument
136 		setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);  in bsec_power_safmem()
139 		clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);  in bsec_power_safmem()
144 	return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,  in bsec_power_safmem()
151  * @base: base address of bsec IP
155 static int bsec_shadow_register(u32 base, u32 otp)  in bsec_shadow_register()  argument
162 	if (bsec_read_SR_lock(base, otp))  in bsec_shadow_register()
166 	val = readl(base + BSEC_OTP_STATUS_OFF);  in bsec_shadow_register()
168 		ret = bsec_power_safmem(base, true);  in bsec_shadow_register()
174 	writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);  in bsec_shadow_register()
177 	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,  in bsec_shadow_register()
183 	ret = bsec_check_error(base, otp);  in bsec_shadow_register()
186 		bsec_power_safmem(base, false);  in bsec_shadow_register()
193  * @base: base address of bsec IP
198 static int bsec_read_shadow(u32 base, u32 *val, u32 otp)  in bsec_read_shadow()  argument
200 	*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));  in bsec_read_shadow()
202 	return bsec_check_error(base, otp);  in bsec_read_shadow()
207  * @base: base address of bsec IP
212 static int bsec_write_shadow(u32 base, u32 val, u32 otp)  in bsec_write_shadow()  argument
215 	if (bsec_read_SW_lock(base, otp))  in bsec_write_shadow()
218 	writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));  in bsec_write_shadow()
220 	return bsec_check_error(base, otp);  in bsec_write_shadow()
225  * @base: base address of bsec IP
231 static int bsec_program_otp(long base, u32 val, u32 otp)  in bsec_program_otp()  argument
236 	if (bsec_read_SP_lock(base, otp))  in bsec_program_otp()
239 	if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))  in bsec_program_otp()
243 	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {  in bsec_program_otp()
244 		ret = bsec_power_safmem(base, true);  in bsec_program_otp()
251 	writel(val, base + BSEC_OTP_WRDATA_OFF);  in bsec_program_otp()
254 	writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);  in bsec_program_otp()
257 	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,  in bsec_program_otp()
266 		ret = bsec_check_error(base, otp);  in bsec_program_otp()
269 		bsec_power_safmem(base, false);  in bsec_program_otp()
276 	u32 base;  member
286 	ret = bsec_read_shadow(plat->base, &tmp_data, otp);  in stm32mp_bsec_read_otp()
291 	ret = bsec_shadow_register(plat->base, otp);  in stm32mp_bsec_read_otp()
295 	ret = bsec_read_shadow(plat->base, val, otp);  in stm32mp_bsec_read_otp()
300 	ret = bsec_write_shadow(plat->base, tmp_data, otp);  in stm32mp_bsec_read_otp()
308 	return bsec_read_shadow(plat->base, val, otp);  in stm32mp_bsec_read_shadow()
315 	return bsec_program_otp(plat->base, val, otp);  in stm32mp_bsec_write_otp()
322 	return bsec_write_shadow(plat->base, val, otp);  in stm32mp_bsec_write_shadow()
403 	plat->base = (u32)dev_read_addr_ptr(dev);  in stm32mp_bsec_ofdata_to_platdata()
424 	.base = STM32_BSEC_BASE,