Lines Matching +full:fpga +full:- +full:bridge

1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/u-boot.h>
34 	const u32 bsel = readl(&sysmgr_regs->bootinfo);  in spl_boot_device()
37 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */  in spl_boot_device()
76 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in socfpga_pl310_clear()
78 	writel(0x111, &pl310->pl310_tag_latency_ctrl);  in socfpga_pl310_clear()
79 	writel(0x121, &pl310->pl310_data_latency_ctrl);  in socfpga_pl310_clear()
82 	setbits_le32(&pl310->pl310_aux_ctrl,  in socfpga_pl310_clear()
88 	ena = readl(&pl310->pl310_ctrl);  in socfpga_pl310_clear()
93 	 * entirely in L1 I-cache to avoid any bus traffic through  in socfpga_pl310_clear()
115 	: "r"(&pl310->pl310_inv_way),  in socfpga_pl310_clear()
116 	  "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)  in socfpga_pl310_clear()
120 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in socfpga_pl310_clear()
134 	reg = readl(&sysmgr_regs->eccgrp_ocram);  in board_init_f()
137 		       &sysmgr_regs->eccgrp_ocram);  in board_init_f()
140 		       &sysmgr_regs->eccgrp_ocram);  in board_init_f()
142 	memset(__bss_start, 0, __bss_end - __bss_start);  in board_init_f()
155 		/* Put FPGA bridges into reset too. */  in board_init_f()
184 	/* De-assert reset for peripherals and bridges based on handoff */  in board_init_f()