Lines Matching +full:0 +full:x0003ffff

22 #define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
29 	u32	dram_timing4;	/* 0x10 */
34 	u32	dram_addrw;	/* 0x2c */
35 	u32	dram_if_width;	/* 0x30 */
39 	u32	sbe_count;	/* 0x40 */
43 	u32	drop_addr;	/* 0x50 */
47 	u32	ctrl_width;	/* 0x60 */
51 	u32	rfifo_cmap;	/* 0x70 */
55 	u32	fpgaport_rst;	/* 0x80 */
59 	u32	prot_rule_addr;	/* 0x90 */
64 	u32	mp_priority;	/* 0xac */
65 	u32	mp_weight0;	/* 0xb0 */
69 	u32	mp_pacing0;	/* 0xc0 */
73 	u32	mp_threshold0;	/* 0xd0 */
77 	u32	phy_ctrl0;	/* 0x150 */
221 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
223 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
225 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
227 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
229 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
231 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
233 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
235 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
236 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
237 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
240 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
242 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
244 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
246 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
248 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
249 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
250 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
253 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
255 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
257 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
259 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
260 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
261 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
264 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
266 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
268 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
270 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
271 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
272 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
275 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
277 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
278 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
279 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
282 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
283 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
284 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
287 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
289 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
291 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
292 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
293 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
295 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
296 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
298 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
299 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
301 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
302 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
304 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
307 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
309 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
310 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
311 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
313 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
314 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
316 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
317 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
319 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
320 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
322 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
323 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
325 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
326 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
328 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
329 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
331 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
332 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
335 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
336 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
337 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
340 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
341 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
342 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
344 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
345 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
347 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
348 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
351 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
352 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
353 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
355 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
356 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
358 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
359 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
361 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
362 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
365 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
366 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
367 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
369 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
370 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
372 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
373 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
376 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
379 0xffffffff
382 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
385 0xffffffff
388 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
391 0x0000ffff
393 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
394 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
399  (((x) << 12) & 0xfffff000)
401  (((x) << 10) & 0x00000c00)
403  (((x) << 6) & 0x000000c0)
405  (((x) << 8) & 0x00000100)
407  (((x) << 9) & 0x00000200)
409  (((x) << 4) & 0x00000030)
411  (((x) << 2) & 0x0000000c)
413  (((x) << 0) & 0x00000003)
417  (((x) << 12) & 0xfffff000)
419  (((x) << 0) & 0x00000fff)
422  (((x) << 0) & 0x00000fff)
425 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
426 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
427 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
429 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
430 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004