26 	writel(val, &clock_manager_base->main_pll.bypass);  in cm_write_bypass_mainpll()
71 		&clock_manager_base->main_pll.pllglob);  in cm_basic_init()
72 	writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);  in cm_basic_init()
73 	writel(vcocalib, &clock_manager_base->main_pll.vcocalib);  in cm_basic_init()
74 	writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);  in cm_basic_init()
75 	writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);  in cm_basic_init()
76 	writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);  in cm_basic_init()
102 	setbits_le32(&clock_manager_base->main_pll.pllglob,  in cm_basic_init()
118 	writel(0xff, &clock_manager_base->main_pll.mpuclk);  in cm_basic_init()
119 	writel(0xff, &clock_manager_base->main_pll.nocclk);  in cm_basic_init()
120 	writel(0xff, &clock_manager_base->main_pll.cntr2clk);  in cm_basic_init()
121 	writel(0xff, &clock_manager_base->main_pll.cntr3clk);  in cm_basic_init()
122 	writel(0xff, &clock_manager_base->main_pll.cntr4clk);  in cm_basic_init()
123 	writel(0xff, &clock_manager_base->main_pll.cntr5clk);  in cm_basic_init()
124 	writel(0xff, &clock_manager_base->main_pll.cntr6clk);  in cm_basic_init()
125 	writel(0xff, &clock_manager_base->main_pll.cntr7clk);  in cm_basic_init()
126 	writel(0xff, &clock_manager_base->main_pll.cntr8clk);  in cm_basic_init()
127 	writel(0xff, &clock_manager_base->main_pll.cntr9clk);  in cm_basic_init()
137 	writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);  in cm_basic_init()
138 	writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);  in cm_basic_init()
139 	writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);  in cm_basic_init()
140 	writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);  in cm_basic_init()
141 	writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);  in cm_basic_init()
142 	writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);  in cm_basic_init()
143 	writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);  in cm_basic_init()
144 	writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);  in cm_basic_init()
145 	writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);  in cm_basic_init()
146 	writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);  in cm_basic_init()
165 	writel(~0, &clock_manager_base->main_pll.en);  in cm_basic_init()
177 	reg = readl(&clock_manager_base->main_pll.pllglob);  in cm_get_main_vco_clk_hz()
196 	reg = readl(&clock_manager_base->main_pll.fdbck);  in cm_get_main_vco_clk_hz()
237 	unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);  in cm_get_mpu_clk_hz()
244 		clock /= (readl(&clock_manager_base->main_pll.pllc0) &  in cm_get_mpu_clk_hz()
267 	clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &  in cm_get_mpu_clk_hz()
274 	u32 clock = readl(&clock_manager_base->main_pll.nocclk);  in cm_get_l3_main_clk_hz()
281 		clock /= (readl(&clock_manager_base->main_pll.pllc1) &  in cm_get_l3_main_clk_hz()
304 	clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &  in cm_get_l3_main_clk_hz()
318 		clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &  in cm_get_mmc_controller_clk_hz()
347 	clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>  in cm_get_l4_sp_clk_hz()
361 	clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>  in cm_get_spi_controller_clk_hz()