188 			  struct perpll_cfg *per_cfg)  in of_get_clk_cfg()  argument
216 					 ARRAY_SIZE(perpll_cfg_tab), per_cfg))  in of_get_clk_cfg()
267 		struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)  in cm_calc_handoff_periph_vco_clk_hz()  argument
272 	switch (per_cfg->vco0_psrc) {  in cm_calc_handoff_periph_vco_clk_hz()
291 	clk_hz /= 1 + per_cfg->vco1_denom;  in cm_calc_handoff_periph_vco_clk_hz()
292 	clk_hz *= 1 + per_cfg->vco1_numer;  in cm_calc_handoff_periph_vco_clk_hz()
299 					       struct perpll_cfg *per_cfg)  in cm_calc_handoff_mpu_clk_hz()  argument
311 		clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);  in cm_calc_handoff_mpu_clk_hz()
335 					       struct perpll_cfg *per_cfg)  in cm_calc_handoff_noc_clk_hz()  argument
347 		clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);  in cm_calc_handoff_noc_clk_hz()
372 				   struct perpll_cfg *per_cfg)  in cm_is_pll_ramp_required()  argument
389 		    (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >  in cm_is_pll_ramp_required()
398 		    (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >  in cm_is_pll_ramp_required()
416 		    (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >  in cm_is_pll_ramp_required()
425 		    (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >  in cm_is_pll_ramp_required()
434 			      struct perpll_cfg *per_cfg,  in cm_calculate_numer()  argument
460 		denom = per_cfg->vco1_denom;  in cm_calculate_numer()
466 		denom = per_cfg->vco1_denom;  in cm_calculate_numer()
485 					   struct perpll_cfg *per_cfg,  in cm_calc_safe_pll_numer()  argument
508 		switch (per_cfg->vco0_psrc) {  in cm_calc_safe_pll_numer()
529 	return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz);  in cm_calc_safe_pll_numer()
534 			     struct perpll_cfg *per_cfg,  in cm_pll_ramp_main()  argument
542 		clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);  in cm_pll_ramp_main()
545 		clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);  in cm_pll_ramp_main()
553 			cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),  in cm_pll_ramp_main()
566 			       struct perpll_cfg *per_cfg,  in cm_pll_ramp_periph()  argument
574 		clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);  in cm_pll_ramp_periph()
577 		clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);  in cm_pll_ramp_periph()
582 		writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |  in cm_pll_ramp_periph()
583 			cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),  in cm_pll_ramp_periph()
588 	writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |  in cm_pll_ramp_periph()
589 		per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);  in cm_pll_ramp_periph()
633 static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)  in cm_full_cfg()  argument
664 	       (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),  in cm_full_cfg()
682 	ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);  in cm_full_cfg()
691 			cm_calc_safe_pll_numer(0, main_cfg, per_cfg,  in cm_full_cfg()
700 	ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);  in cm_full_cfg()
710 		writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |  in cm_full_cfg()
711 			cm_calc_safe_pll_numer(1, main_cfg, per_cfg,  in cm_full_cfg()
715 		writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |  in cm_full_cfg()
716 			per_cfg->vco1_numer,  in cm_full_cfg()
775 	writel(per_cfg->cntr2clk_cnt |  in cm_full_cfg()
776 	       (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),  in cm_full_cfg()
779 	writel(per_cfg->cntr3clk_cnt |  in cm_full_cfg()
780 	       (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),  in cm_full_cfg()
783 	writel(per_cfg->cntr4clk_cnt |  in cm_full_cfg()
784 	       (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),  in cm_full_cfg()
787 	writel(per_cfg->cntr5clk_cnt |  in cm_full_cfg()
788 	       (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),  in cm_full_cfg()
791 	writel(per_cfg->cntr6clk_cnt |  in cm_full_cfg()
792 	       (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),  in cm_full_cfg()
795 	writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);  in cm_full_cfg()
797 	writel(per_cfg->cntr8clk_cnt |  in cm_full_cfg()
798 	       (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),  in cm_full_cfg()
801 	writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);  in cm_full_cfg()
826 	writel(per_cfg->gpiodiv_gpiodbclk,  in cm_full_cfg()
830 	writel((per_cfg->emacctl_emac0sel <<  in cm_full_cfg()
832 	       (per_cfg->emacctl_emac1sel <<  in cm_full_cfg()
834 	       (per_cfg->emacctl_emac2sel <<  in cm_full_cfg()
879 		cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);  in cm_full_cfg()
881 		cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);  in cm_full_cfg()
911 	struct perpll_cfg per_cfg;  in cm_basic_init()  local
916 	memset(&per_cfg, 0, sizeof(per_cfg));  in cm_basic_init()
918 	rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg);  in cm_basic_init()
924 	return cm_full_cfg(&main_cfg, &per_cfg);  in cm_basic_init()