554 			&clock_manager_base->main_pll.vco1);  in cm_pll_ramp_main()
559 		main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);  in cm_pll_ramp_main()
641 		&clock_manager_base->main_pll.enr);  in cm_full_cfg()
648 	       &clock_manager_base->main_pll.bypasss);  in cm_full_cfg()
660 	       &clock_manager_base->main_pll.vco0);  in cm_full_cfg()
667 	writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);  in cm_full_cfg()
693 			&clock_manager_base->main_pll.vco1);  in cm_full_cfg()
697 			&clock_manager_base->main_pll.vco1);  in cm_full_cfg()
723 	clrbits_le32(&clock_manager_base->main_pll.vco0,  in cm_full_cfg()
734 	writel((readl(&clock_manager_base->main_pll.vco0) &  in cm_full_cfg()
737 		&clock_manager_base->main_pll.vco0);  in cm_full_cfg()
750 	writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);  in cm_full_cfg()
752 	writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);  in cm_full_cfg()
754 	writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);  in cm_full_cfg()
756 	writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);  in cm_full_cfg()
758 	writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);  in cm_full_cfg()
762 	       &clock_manager_base->main_pll.cntr7clk);  in cm_full_cfg()
764 	writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);  in cm_full_cfg()
768 	       &clock_manager_base->main_pll.cntr9clk);  in cm_full_cfg()
771 	       &clock_manager_base->main_pll.cntr15clk);  in cm_full_cfg()
807 	       &clock_manager_base->main_pll.mpuclk);  in cm_full_cfg()
811 	       &clock_manager_base->main_pll.nocclk);  in cm_full_cfg()
824 		&clock_manager_base->main_pll.nocdiv);  in cm_full_cfg()
846 	setbits_le32(&clock_manager_base->main_pll.vco0,  in cm_full_cfg()
852 	clrbits_le32(&clock_manager_base->main_pll.vco0,  in cm_full_cfg()
861 	       &clock_manager_base->main_pll.bypassr);  in cm_full_cfg()
886 		&clock_manager_base->main_pll.ens);  in cm_full_cfg()