15 #define SMC_DATA16_WIDTH(x)    (1<<((x*4)+0))  argument
16 #define SMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/  argument
18 #define SMC_WAIT_ENABLE(x)     (1<<((x*4)+2))  argument
19 #define SMC_BYTE_ENABLE(x)     (1<<((x*4)+3))  argument
21 #define SMC_BC_TACS(x) (x << 28) /* 0clk     address set-up */  argument
22 #define SMC_BC_TCOS(x) (x << 24) /* 4clk     chip selection set-up */  argument
23 #define SMC_BC_TACC(x) (x << 16) /* 14clk    access cycle */  argument
24 #define SMC_BC_TCOH(x) (x << 12) /* 1clk     chip selection hold */  argument
25 #define SMC_BC_TAH(x)  (x << 8)  /* 4clk     address holding time */  argument
26 #define SMC_BC_TACP(x) (x << 4)  /* 6clk     page mode access cycle */  argument
27 #define SMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */  argument