74 	for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)  in spl_decode_boot_device()
101 	chosen = fdt_find_or_add_subnode(blob, 0, "chosen");  in spl_perform_fixups()
102 	if (chosen < 0) {  in spl_perform_fixups()
110 #define TIMER_CHN10_BASE	0xff8680a0
111 #define TIMER_END_COUNT_L	0x00
112 #define TIMER_END_COUNT_H	0x04
113 #define TIMER_INIT_COUNT_L	0x10
114 #define TIMER_INIT_COUNT_H	0x14
115 #define TIMER_CONTROL_REG	0x1c
117 #define TIMER_EN	0x1
118 #define	TIMER_FMODE	(0 << 1)
123 	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);  in secure_timer_init()
124 	writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);  in secure_timer_init()
125 	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);  in secure_timer_init()
126 	writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);  in secure_timer_init()
132 #define GRF_BASE	0xff770000  in board_debug_uart_init()
133 #define GPIO0_BASE	0xff720000  in board_debug_uart_init()
134 #define PMUGRF_BASE	0xff320000  in board_debug_uart_init()
141 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)  in board_debug_uart_init()
151 	rk_setreg(&grf->io_vsel, 1 << 0);  in board_debug_uart_init()
198 	sum = 0;  in board_init_f()
199 	for (i = 0; i < 150000; i++)  in board_init_f()
209 	 * printhex8(0x1234);  in board_init_f()
225 	 * 0x0 through 0xfffff (i.e. the first MB of memory) will  in board_init_f()
231 	rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);  in board_init_f()
232 	rk_clrreg(&sgrf->slv_secure_con4, 0x2000);  in board_init_f()
236 	rk_clrreg(&grf->emmccore_con[11], 0x0ff);  in board_init_f()
240 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);  in board_init_f()
246 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);  in board_init_f()
259 	return 0;  in board_fit_config_name_match()