Lines Matching +full:rk3036 +full:- +full:cru
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
17 * (due to 4K SRAM size limits), so these are hard-coded
26 struct rk3036_cru *cru; member
277 * 100: lpddr2-s2
278 * 101: lpddr2-s4
319 * rk3036 only support 16bit
329 struct rk3036_pll *pll = &priv->cru->pll[1]; in rkdclk_init()
331 /* pll enter slow-mode */ in rkdclk_init()
332 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
336 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()
338 rk_clrsetreg(&pll->con0, in rkdclk_init()
342 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()
347 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkdclk_init()
350 /* PLL enter normal-mode */ in rkdclk_init()
351 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
368 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_pctrl_reset()
370 rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
378 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | in phy_pctrl_reset()
382 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
386 clrsetbits_le32(&ddr_phy->ddrphy_reg1, in phy_pctrl_reset()
390 clrsetbits_le32(&ddr_phy->ddrphy_reg1, in phy_pctrl_reset()
399 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_dll_bypass_set()
403 LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a); in phy_dll_bypass_set()
408 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6); in phy_dll_bypass_set()
414 &ddr_phy->ddrphy_reg9); in phy_dll_bypass_set()
417 LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a); in phy_dll_bypass_set()
423 &ddr_phy->ddrphy_reg6); in phy_dll_bypass_set()
429 &ddr_phy->ddrphy_reg9); in phy_dll_bypass_set()
434 CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19); in phy_dll_bypass_set()
438 LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8); in phy_dll_bypass_set()
440 RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11); in phy_dll_bypass_set()
446 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
448 while (readl(&pctl->mcmd) & START_CMD) in send_command()
454 struct rk3036_ddr_pctl *pctl = priv->pctl; in memory_init()
484 struct rk3036_ddr_phy *ddr_phy = priv->phy; in data_training()
485 struct rk3036_ddr_pctl *pctl = priv->pctl; in data_training()
489 value = readl(&pctl->trefi), in data_training()
490 writel(0, &pctl->trefi); in data_training()
492 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, in data_training()
496 while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != in data_training()
501 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, in data_training()
512 writel(value, &pctl->trefi); in data_training()
518 struct rk3036_ddr_pctl *pctl = priv->pctl; in move_to_config_state()
521 state = readl(&pctl->stat) & PCTL_STAT_MASK; in move_to_config_state()
524 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
525 while ((readl(&pctl->stat) & PCTL_STAT_MASK) in move_to_config_state()
535 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
536 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) in move_to_config_state()
550 struct rk3036_ddr_pctl *pctl = priv->pctl; in move_to_access_state()
553 state = readl(&pctl->stat) & PCTL_STAT_MASK; in move_to_access_state()
556 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
557 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) in move_to_access_state()
561 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
562 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) in move_to_access_state()
566 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
567 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) in move_to_access_state()
580 struct rk3036_ddr_pctl *pctl = priv->pctl; in pctl_cfg()
584 writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); in pctl_cfg()
585 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); in pctl_cfg()
586 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in pctl_cfg()
588 &pctl->dfilpcfg0); in pctl_cfg()
590 writel(1, &pctl->dfitphyupdtype0); in pctl_cfg()
591 writel(0x0d, &pctl->dfitphyrdlat); in pctl_cfg()
595 &pctl->dfiodtcfg); in pctl_cfg()
598 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); in pctl_cfg()
601 writel(0, &pctl->dfiupdcfg); in pctl_cfg()
608 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
610 reg = readl(&pctl->tcl); in pctl_cfg()
611 writel(reg - 3, &pctl->dfitrddataen); in pctl_cfg()
612 reg = readl(&pctl->tcwl); in pctl_cfg()
613 writel(reg - 1, &pctl->dfitphywrlat); in pctl_cfg()
618 &pctl->mcfg); in pctl_cfg()
620 writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2); in pctl_cfg()
621 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); in pctl_cfg()
626 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_cfg()
627 struct rk3036_service_sys *axi_bus = priv->axi_bus; in phy_cfg()
629 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
630 writel(0x3f, &axi_bus->readlatency); in phy_cfg()
633 &ddr_phy->ddrphy_reg2); in phy_cfg()
635 clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl); in phy_cfg()
636 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
637 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16); in phy_cfg()
638 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22); in phy_cfg()
639 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25); in phy_cfg()
640 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26); in phy_cfg()
641 writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27); in phy_cfg()
642 writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28); in phy_cfg()
649 struct rk3036_ddr_config config = priv->ddr_config; in dram_cfg_rbc()
650 struct rk3036_service_sys *axi_bus = priv->axi_bus; in dram_cfg_rbc()
656 noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | in dram_cfg_rbc()
657 1 << 3 | (config.col - 10); in dram_cfg_rbc()
667 noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | in dram_cfg_rbc()
668 (config.col - 10); in dram_cfg_rbc()
676 noc_config = 1 << 6 | (config.cs0_row - 13) << 4 | in dram_cfg_rbc()
677 2 << 1 | (config.col - 10); in dram_cfg_rbc()
684 noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 | in dram_cfg_rbc()
685 (config.col - 10); in dram_cfg_rbc()
694 writel(i, &axi_bus->ddrconf); in dram_cfg_rbc()
702 struct rk3036_ddr_config config = priv->ddr_config; in sdram_all_config()
705 cs1_row = config.cs1_row - 13; in sdram_all_config()
709 (config.rank - 1) << DDR_RANK_CNT_SHIFT | in sdram_all_config()
710 (config.col - 9) << DDR_COL_SHIFT | in sdram_all_config()
712 (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT | in sdram_all_config()
716 writel(os_reg, &priv->grf->os_reg[1]); in sdram_all_config()
724 os_reg = readl(&grf->os_reg[1]); in sdram_size()
729 bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK); in sdram_size()
732 /* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */ in sdram_size()
736 size += size >> (cs0_row - cs1_row); in sdram_size()
745 sdram_priv.cru = (void *)CRU_BASE; in sdram_init()
758 writel(POWER_UP_START, &sdram_priv.pctl->powctl); in sdram_init()
759 while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE)) in sdram_init()