Lines Matching +full:0 +full:x10100

11 #define OHCI_OFFSET	0x00
12 #define OHCI_SIZE	0x1000
13 #define EHCI_OFFSET	0x1000
14 #define EHCI_SIZE	0x1000
16 #define EHCI_USBCMD	(EHCI_OFFSET + 0x0020)
22 #define USBH_RST	(1 << 0)
31 #define PCIAHB_WIN_PREFETCH	((1 << 1)|(1 << 0))
35 #define AHB_CFG_AHBPCI		0x40000000
36 #define AHB_CFG_HOST		0x80000000
55 #define MMODE_HTRANS		(1 << 0)
58 #define PCIBUS_PARK_TIMER       0x00FF0000
59 #define PCIBUS_PARK_TIMER_SET   0x00070000
68 #define PCIREQ0                 (1 << 0)
70 #define SMSTPCR7        0xE615014C
78 #define USBCTR_WIN_SIZE_1GB	0x800
81 #define PCI_CONF_OHCI_OFFSET	0x10000
82 #define PCI_CONF_EHCI_OFFSET	0x10100
92 #define PCI_CONF_AHBPCI_OFFSET	0x10000
94 	u32 vid_did;		/* 0x00 */
98 	u32 basead;		/* 0x10 */
102 	u32 ssvdi_ssid;		/* 0x2C */
108 #define AHBPCI_OFFSET	0x10800
110 	u32 pciahb_win1_ctr;	/* 0x00 */
114 	u32 ahbpci_win1_ctr;	/* 0x10 */
118 	u32 pci_int_enable;	/* 0x20 */
121 	u32 ahb_bus_ctr;	/* 0x30 */
124 	u32 pci_arbiter_ctr;	/* 0x40 */
126 	u32 pci_unit_rev;	/* 0x48 */