1 // SPDX-License-Identifier: GPL-2.0+
21  * exported are weakly linked so that they can be over-ridden in the board
25  * For any new board with different memory devices over-ride one or more
27  * - emif_get_reg_dump()
28  * - emif_get_dmm_regs()
29  * - emif_get_device_details()
30  * - emif_get_device_timings()
147 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)  in emif_get_reg_dump_sdp()  argument
151 		*regs = &emif_regs_532_mhz_2cs;  in emif_get_reg_dump_sdp()
154 		*regs = &emif_regs_ddr3_532_mhz_1cs;  in emif_get_reg_dump_sdp()
157 		*regs = &emif_regs_532_mhz_2cs_es2;  in emif_get_reg_dump_sdp()
161 		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;  in emif_get_reg_dump_sdp()
166 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
280 /* Ext phy ctrl 1-35 regs */
320 /* Ext phy ctrl 1-35 regs */
360 /* Ext phy ctrl 1-35 regs */
448 					     const u32 **regs,  in emif_get_ext_phy_ctrl_const_regs()  argument
454 		*regs = ext_phy_ctrl_const_base;  in emif_get_ext_phy_ctrl_const_regs()
458 		*regs = ddr3_ext_phy_ctrl_const_base_es1;  in emif_get_ext_phy_ctrl_const_regs()
462 		*regs = ddr3_ext_phy_ctrl_const_base_es2;  in emif_get_ext_phy_ctrl_const_regs()
469 			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;  in emif_get_ext_phy_ctrl_const_regs()
473 			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;  in emif_get_ext_phy_ctrl_const_regs()
479 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;  in emif_get_ext_phy_ctrl_const_regs()
487 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;  in emif_get_ext_phy_ctrl_const_regs()
491 		*regs = ddr3_ext_phy_ctrl_const_base_es2;  in emif_get_ext_phy_ctrl_const_regs()
497 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)  in get_lpddr2_mr_regs()  argument
499 	*regs = &mr_regs;  in get_lpddr2_mr_regs()
502 static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)  in do_ext_phy_settings_omap5()  argument
515 	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);  in do_ext_phy_settings_omap5()
516 	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);  in do_ext_phy_settings_omap5()
526 	 * external phy 6-24 registers do not change with  in do_ext_phy_settings_omap5()
541 static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)  in do_ext_phy_settings_dra7()  argument
551 	hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;  in do_ext_phy_settings_dra7()
552 	phy = regs->emif_ddr_phy_ctlr_1_init;  in do_ext_phy_settings_dra7()
554 	emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);  in do_ext_phy_settings_dra7()
603 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)  in do_ext_phy_settings()  argument
606 		do_ext_phy_settings_omap5(base, regs);  in do_ext_phy_settings()
608 		do_ext_phy_settings_dra7(base, regs);  in do_ext_phy_settings()