Lines Matching refs:NUM_SYS_CLKS

31 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
42 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
53 			core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
64 			core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
75 		core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
85 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
95 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
105 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
115 static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
125 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
135 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
148 		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
168 		abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
178 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
188 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
198 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
208 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {