Lines Matching +full:pmic +full:- +full:32 +full:k
1 // SPDX-License-Identifier: GPL-2.0+
36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
65 * dpll locked at 1200 MHz - MPU clk at 600 MHz
69 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
70 {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
71 {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
72 {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
73 {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
74 {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
75 {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
81 {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
82 {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
83 {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
84 {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
85 {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
86 {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
87 {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
92 {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
93 {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
94 {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
95 {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
96 {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
97 {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
98 {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
104 {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
105 {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
106 {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
107 {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
108 {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
109 {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
110 {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
114 {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
115 {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
116 {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
117 {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
118 {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
119 {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
120 {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
124 {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
125 {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
126 {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
127 {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
128 {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
129 {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
130 {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
137 {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
138 {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
139 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
140 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
141 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
142 {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
143 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
146 /* ABE M & N values with 32K clock as source */
148 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
153 {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
154 {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
155 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
156 {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
157 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
158 {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
159 {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
242 /* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
267 .mpu.pmic = &twl6030_4430es1,
271 .core.pmic = &twl6030_4430es1,
275 .mm.pmic = &twl6030_4430es1,
281 .mpu.pmic = &twl6030,
285 .core.pmic = &twl6030,
289 .mm.pmic = &twl6030,
295 .mpu.pmic = &tps62361,
299 .core.pmic = &twl6030,
303 .mm.pmic = &twl6030,
313 .mpu.pmic = &twl6030,
317 .core.pmic = &twl6030,
321 .mm.pmic = &twl6030,
331 (*prcm)->cm_l4per_clkstctrl, in enable_basic_clocks()
332 (*prcm)->cm_l3init_clkstctrl, in enable_basic_clocks()
333 (*prcm)->cm_memif_clkstctrl, in enable_basic_clocks()
334 (*prcm)->cm_l4cfg_clkstctrl, in enable_basic_clocks()
339 (*prcm)->cm_l3_gpmc_clkctrl, in enable_basic_clocks()
340 (*prcm)->cm_memif_emif_1_clkctrl, in enable_basic_clocks()
341 (*prcm)->cm_memif_emif_2_clkctrl, in enable_basic_clocks()
342 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, in enable_basic_clocks()
343 (*prcm)->cm_wkup_gpio1_clkctrl, in enable_basic_clocks()
344 (*prcm)->cm_l4per_gpio2_clkctrl, in enable_basic_clocks()
345 (*prcm)->cm_l4per_gpio3_clkctrl, in enable_basic_clocks()
346 (*prcm)->cm_l4per_gpio4_clkctrl, in enable_basic_clocks()
347 (*prcm)->cm_l4per_gpio5_clkctrl, in enable_basic_clocks()
348 (*prcm)->cm_l4per_gpio6_clkctrl, in enable_basic_clocks()
353 (*prcm)->cm_wkup_gptimer1_clkctrl, in enable_basic_clocks()
354 (*prcm)->cm_l3init_hsmmc1_clkctrl, in enable_basic_clocks()
355 (*prcm)->cm_l3init_hsmmc2_clkctrl, in enable_basic_clocks()
356 (*prcm)->cm_l4per_gptimer2_clkctrl, in enable_basic_clocks()
357 (*prcm)->cm_wkup_wdtimer2_clkctrl, in enable_basic_clocks()
358 (*prcm)->cm_l4per_uart3_clkctrl, in enable_basic_clocks()
359 (*prcm)->cm_l4per_i2c1_clkctrl, in enable_basic_clocks()
360 (*prcm)->cm_l4per_i2c2_clkctrl, in enable_basic_clocks()
361 (*prcm)->cm_l4per_i2c3_clkctrl, in enable_basic_clocks()
362 (*prcm)->cm_l4per_i2c4_clkctrl, in enable_basic_clocks()
367 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, in enable_basic_clocks()
371 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, in enable_basic_clocks()
373 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, in enable_basic_clocks()
376 /* Select 32KHz clock as the source of GPTIMER1 */ in enable_basic_clocks()
377 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, in enable_basic_clocks()
381 setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, in enable_basic_clocks()
384 /* Enable 32 KHz clock for USB PHY */ in enable_basic_clocks()
385 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, in enable_basic_clocks()
401 (*prcm)->cm_l3init_hsusbotg_clkctrl, in enable_basic_uboot_clocks()
402 (*prcm)->cm_l3init_usbphy_clkctrl, in enable_basic_uboot_clocks()
403 (*prcm)->cm_clksel_usb_60mhz, in enable_basic_uboot_clocks()
404 (*prcm)->cm_l3init_hsusbtll_clkctrl, in enable_basic_uboot_clocks()
409 (*prcm)->cm_l4per_mcspi1_clkctrl, in enable_basic_uboot_clocks()
410 (*prcm)->cm_l3init_hsusbhost_clkctrl, in enable_basic_uboot_clocks()