57 		/* SYS_CLKSEL - 1 to match the dpll param array indices */  in __get_sys_clk_index()
116 		printf("Bypassing DPLL failed %x\n", base);  in wait_for_bypass()
135 		printf("DPLL locking failed for %x\n", base);  in wait_for_lock()
211 				u8 lock, char *dpll)  in do_setup_dpll()  argument
223 		 * The Dpll has already been locked by rom code using CH.  in do_setup_dpll()
230 			debug("\n %s Dpll locked, but not for ideal M = %d,"  in do_setup_dpll()
232 				"N= %d" , dpll, params->m, params->n,  in do_setup_dpll()
235 			/* Dpll locked with ideal values for nominal opps. */  in do_setup_dpll()
236 			debug("\n %s Dpll already locked with ideal"  in do_setup_dpll()
237 						"nominal opp values", dpll);  in do_setup_dpll()
262 	/* Wait till the DPLL locks */  in do_setup_dpll()
279 	/* Find Core DPLL locked frequency first */  in omap_ddr_clk()
305  * Lock MPU dpll
340 	debug("MPU DPLL locked\n");  in configure_mpu_dpll()
353 	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction  in setup_usb_dpll()
368 	/* Now setup the dpll with the regular function */  in setup_usb_dpll()
381 	/* CORE dpll */  in setup_dplls()
384 	 * Do not lock the core DPLL now. Just set it up.  in setup_dplls()
385 	 * Core DPLL will be locked after setting up EMIF  in setup_dplls()
400 	debug("Core DPLL configured\n");  in setup_dplls()
402 	/* lock PER dpll */  in setup_dplls()
406 	debug("PER DPLL locked\n");  in setup_dplls()
408 	/* MPU dpll */  in setup_dplls()