Lines Matching refs:DDRPHY_CONFIG_BASE
29 writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
30 writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
31 writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
32 writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS in ddr_init_settings()
37 writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */ in ddr_init_settings()
38 writel(0x1, DDRPHY_CONFIG_BASE + 0x104); in ddr_init_settings()
39 writel(0x1, DDRPHY_CONFIG_BASE + 0x19C); in ddr_init_settings()
40 writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8); in ddr_init_settings()
41 writel(0x1, DDRPHY_CONFIG_BASE + 0x240); in ddr_init_settings()
42 writel(0x1, DDRPHY_CONFIG_BASE + 0x24C); in ddr_init_settings()
43 writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4); in ddr_init_settings()
44 writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0); in ddr_init_settings()
56 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */ in ddr_init_settings()
57 writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */ in ddr_init_settings()
58 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */ in ddr_init_settings()
59 writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */ in ddr_init_settings()
60 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */ in ddr_init_settings()
61 writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */ in ddr_init_settings()
62 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */ in ddr_init_settings()
63 writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */ in ddr_init_settings()
66 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */ in ddr_init_settings()
67 writel(0x0, DDRPHY_CONFIG_BASE + 0x100); in ddr_init_settings()
68 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */ in ddr_init_settings()
69 writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4); in ddr_init_settings()
70 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */ in ddr_init_settings()
71 writel(0x0, DDRPHY_CONFIG_BASE + 0x248); in ddr_init_settings()
72 writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */ in ddr_init_settings()
73 writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC); in ddr_init_settings()
75 writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */ in ddr_init_settings()
76 writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */ in ddr_init_settings()
77 writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */ in ddr_init_settings()
78 writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */ in ddr_init_settings()
79 writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */ in ddr_init_settings()
80 writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */ in ddr_init_settings()
81 writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */ in ddr_init_settings()
82 writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */ in ddr_init_settings()
83 writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */ in ddr_init_settings()
84 writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */ in ddr_init_settings()
85 writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */ in ddr_init_settings()
86 writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */ in ddr_init_settings()
87 writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */ in ddr_init_settings()
88 writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */ in ddr_init_settings()
94 writel(0x6, (DDRPHY_CONFIG_BASE + 0x358)); in ddr3_sw_levelling()
96 writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108)); in ddr3_sw_levelling()
97 writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC)); in ddr3_sw_levelling()
98 writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250)); in ddr3_sw_levelling()
99 writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4)); in ddr3_sw_levelling()
101 writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC)); in ddr3_sw_levelling()
102 writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180)); in ddr3_sw_levelling()
103 writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224)); in ddr3_sw_levelling()
104 writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8)); in ddr3_sw_levelling()
106 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120)); in ddr3_sw_levelling()
107 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4)); in ddr3_sw_levelling()
108 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268)); in ddr3_sw_levelling()
109 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C)); in ddr3_sw_levelling()
111 writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8)); in ddr3_sw_levelling()
112 writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C)); in ddr3_sw_levelling()
113 writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210)); in ddr3_sw_levelling()
114 writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4)); in ddr3_sw_levelling()