17 static struct emif_reg_struct *emif_reg[2] = {  variable
43 	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);  in get_mr()
45 	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);  in get_mr()
58 	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);  in set_mr()
59 	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);  in set_mr()
83 	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);  in config_sdram_emif4d5()
84 	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);  in config_sdram_emif4d5()
85 	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);  in config_sdram_emif4d5()
87 	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);  in config_sdram_emif4d5()
89 	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);  in config_sdram_emif4d5()
91 	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);  in config_sdram_emif4d5()
92 	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);  in config_sdram_emif4d5()
94 	       &emif_reg[nr]->emif_rd_wr_exec_thresh);  in config_sdram_emif4d5()
102 		writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);  in config_sdram_emif4d5()
103 		writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);  in config_sdram_emif4d5()
104 		writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);  in config_sdram_emif4d5()
105 		writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);  in config_sdram_emif4d5()
113 	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);  in config_sdram_emif4d5()
114 	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);  in config_sdram_emif4d5()
115 	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);  in config_sdram_emif4d5()
117 	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,  in config_sdram_emif4d5()
120 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);  in config_sdram_emif4d5()
126 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);  in config_sdram_emif4d5()
127 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);  in config_sdram_emif4d5()
131 		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |  in config_sdram_emif4d5()
132 		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);  in config_sdram_emif4d5()
133 		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |  in config_sdram_emif4d5()
134 		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);  in config_sdram_emif4d5()
136 		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);  in config_sdram_emif4d5()
139 		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);  in config_sdram_emif4d5()
145 		while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)  in config_sdram_emif4d5()
150 		if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)  in config_sdram_emif4d5()
166 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);  in config_sdram()
167 	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);  in config_sdram()
168 	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);  in config_sdram()
169 	writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */  in config_sdram()
170 	writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */  in config_sdram()
171 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);  in config_sdram()
174 		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);  in config_sdram()
176 		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);  in config_sdram()
179 		writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);  in config_sdram()
184 		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);  in config_sdram()
185 		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);  in config_sdram()
187 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);  in config_sdram()
188 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);  in config_sdram()
189 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);  in config_sdram()
193 		writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);  in config_sdram()
202 	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);  in set_sdram_timings()
203 	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);  in set_sdram_timings()
204 	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);  in set_sdram_timings()
205 	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);  in set_sdram_timings()
206 	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);  in set_sdram_timings()
207 	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);  in set_sdram_timings()
223 			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);  in ext_phy_settings_swlvl()
259 	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);  in ext_phy_settings_hwlvl()
260 	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);  in ext_phy_settings_hwlvl()
261 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);  in ext_phy_settings_hwlvl()
262 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);  in ext_phy_settings_hwlvl()
263 	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);  in ext_phy_settings_hwlvl()
264 	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);  in ext_phy_settings_hwlvl()
265 	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);  in ext_phy_settings_hwlvl()
266 	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);  in ext_phy_settings_hwlvl()
267 	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);  in ext_phy_settings_hwlvl()
268 	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);  in ext_phy_settings_hwlvl()
269 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);  in ext_phy_settings_hwlvl()
270 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);  in ext_phy_settings_hwlvl()
271 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);  in ext_phy_settings_hwlvl()
272 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);  in ext_phy_settings_hwlvl()
273 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);  in ext_phy_settings_hwlvl()
274 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);  in ext_phy_settings_hwlvl()
275 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);  in ext_phy_settings_hwlvl()
276 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);  in ext_phy_settings_hwlvl()
277 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);  in ext_phy_settings_hwlvl()
278 	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);  in ext_phy_settings_hwlvl()
279 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);  in ext_phy_settings_hwlvl()
280 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);  in ext_phy_settings_hwlvl()
281 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);  in ext_phy_settings_hwlvl()
282 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);  in ext_phy_settings_hwlvl()
283 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);  in ext_phy_settings_hwlvl()
284 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);  in ext_phy_settings_hwlvl()
285 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);  in ext_phy_settings_hwlvl()
286 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);  in ext_phy_settings_hwlvl()
287 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);  in ext_phy_settings_hwlvl()
288 	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);  in ext_phy_settings_hwlvl()
289 	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);  in ext_phy_settings_hwlvl()
290 	writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);  in ext_phy_settings_hwlvl()
296 	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);  in ext_phy_settings_hwlvl()
297 	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);  in ext_phy_settings_hwlvl()
298 	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);  in ext_phy_settings_hwlvl()
314 		&emif_reg[nr]->emif_sdram_ref_ctrl);  in config_ddr_phy()
317 		&emif_reg[nr]->emif_ddr_phy_ctrl_1);  in config_ddr_phy()
319 		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);  in config_ddr_phy()
321 	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {  in config_ddr_phy()