1 // SPDX-License-Identifier: GPL-2.0+
7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
20 #include <asm/arch/clock.h>
49 	/* dram_init must store complete ramsize in gd->ram_size */  in dram_init()
50 	gd->ram_size = get_ram_size(  in dram_init()
58 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;  in dram_init_banksize()
59 	gd->bd->bi_dram[0].size = gd->ram_size;  in dram_init_banksize()
67 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
70 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
73 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
75 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
77 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
79 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
156 	ret = omap_mmc_init(0, 0, 0, -1, -1);  in cpu_mmc_init()
160 	return omap_mmc_init(1, 0, 0, -1, -1);  in cpu_mmc_init()
165  * RTC only with DDR in self-refresh mode magic value, checked against during
171 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
190 	.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
200 	.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
210 	{ "ti-musb-peripheral", &usb0 },
212 	{ "ti-musb-host", &usb0 },
215 	{ "ti-musb-peripheral", &usb1 },
217 	{ "ti-musb-host", &usb1 },
247 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);  in am33xx_otg0_set_phy_power()
266 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);  in am33xx_otg1_set_phy_power()
331 	writel(RTC_KICK0R_WE, &rtc->kick0r);  in rtc32k_unlock()
332 	writel(RTC_KICK1R_WE, &rtc->kick1r);  in rtc32k_unlock()
359 	writel(magic, &rtc->scratch1);  in update_rtc_magic()
364  * In the case of non-SPL based booting we'll want to call these
379  * This function is the place to do per-board things such as ramp up the
380  * MPU clock frequency.
394 	writel((1 << 3) | (1 << 6), &rtc->osc);  in rtc32k_enable()
403 	regval = readl(&uart_base->uartsyscfg);  in uart_soft_reset()
405 	writel(regval, &uart_base->uartsyscfg);  in uart_soft_reset()
406 	while ((readl(&uart_base->uartsyssts) &  in uart_soft_reset()
411 	regval = readl(&uart_base->uartsyscfg);  in uart_soft_reset()
413 	writel(regval, &uart_base->uartsyscfg);  in uart_soft_reset()
420 	writel(0xAAAA, &wdtimer->wdtwspr);  in watchdog_disable()
421 	while (readl(&wdtimer->wdtwwps) != 0x0)  in watchdog_disable()
423 	writel(0x5555, &wdtimer->wdtwspr);  in watchdog_disable()
424 	while (readl(&wdtimer->wdtwwps) != 0x0)  in watchdog_disable()
430  * Check if we are executing rtc-only + DDR mode, and resume from it if needed
441 	scratch1 = readl(&rtc->scratch1);  in rtc_only()
446 	 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:  in rtc_only()
447 	 * bits 0-15:  RTC_MAGIC_VAL  in rtc_only()
448 	 * bits 16-31: board type (needed for sdram_init)  in rtc_only()
456 	writel(0, &rtc->scratch1);  in rtc_only()
467 	 * are resuming from self-refresh. This avoids an unnecessary re-init  in rtc_only()
468 	 * of the DDR. The re-init takes time and we would need to wait for  in rtc_only()
471 	writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);  in rtc_only()
476 	/* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */  in rtc_only()
477 	writel(0, &prm_device->emif_ctrl);  in rtc_only()
479 	resume_func = (void *)readl(&rtc->scratch0);  in rtc_only()
527 	/* Enable RTC32K clock */  in early_system_init()
539 	/* dram_init must store complete ramsize in gd->ram_size */  in board_init_f()
540 	gd->ram_size = get_ram_size(  in board_init_f()