Lines Matching +full:0 +full:x10100
16 #define INTREG_BASE 0xd0000000
18 #define KW_OFFSET_REG (INTREG_BASE + 0x20080)
21 #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
22 #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
24 #define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
25 #define KW_TWSI_BASE (KW_REGISTER(0x11000))
26 #define KW_UART0_BASE (KW_REGISTER(0x12000))
27 #define KW_UART1_BASE (KW_REGISTER(0x12100))
28 #define KW_MPP_BASE (KW_REGISTER(0x10000))
29 #define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
30 #define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140))
31 #define KW_RTC_BASE (KW_REGISTER(0x10300))
32 #define KW_NANDF_BASE (KW_REGISTER(0x10418))
33 #define MVEBU_SPI_BASE (KW_REGISTER(0x10600))
34 #define KW_CPU_WIN_BASE (KW_REGISTER(0x20000))
35 #define KW_CPU_REG_BASE (KW_REGISTER(0x20100))
36 #define MVEBU_TIMER_BASE (KW_REGISTER(0x20300))
37 #define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))
38 #define KW_USB20_BASE (KW_REGISTER(0x50000))
39 #define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
40 #define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
41 #define KW_SATA_BASE (KW_REGISTER(0x80000))
42 #define KW_SDIO_BASE (KW_REGISTER(0x90000))
45 #define KW_SATA_PORT0_OFFSET 0x2000
46 #define KW_SATA_PORT1_OFFSET 0x4000