Lines Matching refs:KS2_DEVICE_STATE_CTRL_BASE
154 #define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 macro
155 #define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
156 #define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
157 #define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
158 #define KS2_ETHERNET_CFG (KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
169 #define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
170 #define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
175 #define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
176 #define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
177 #define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
178 #define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
179 #define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
180 #define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
181 #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
182 #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
183 #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
184 #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
185 #define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390)
186 #define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394)
269 #define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
270 #define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
271 #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
312 #define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)