1 // SPDX-License-Identifier: GPL-2.0+
3  * Keystone2: pll initialization
5  * (C) Copyright 2012-2014
46 		if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))  in wait_for_completion()
53 	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |  in bypass_main_pll()
64 	pllm = data->pll_m - 1;  in configure_mult_div()
65 	plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;  in configure_mult_div()
68 	if (data->pll == MAIN_PLL)  in configure_mult_div()
69 		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);  in configure_mult_div()
71 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
76 	bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */  in configure_mult_div()
77 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
82 	clrsetbits_le32(keystone_pll_regs[data->pll].reg1,  in configure_mult_div()
86 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
95 	pllod = data->pll_od - 1;  in configure_main_pll()
100 	tmp = pllctl_reg_read(data->pll, secctl);  in configure_main_pll()
104 		setbits_le32(keystone_pll_regs[data->pll].reg1,  in configure_main_pll()
109 		/* Powerdown and powerup Main Pll */  in configure_main_pll()
110 		pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);  in configure_main_pll()
111 		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);  in configure_main_pll()
115 		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);  in configure_main_pll()
123 	pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,  in configure_main_pll()
130 			offset = pllctl_reg(data->pll, div1) + i;  in configure_main_pll()
132 			offset = pllctl_reg(data->pll, div4) + (i - 3);  in configure_main_pll()
134 		if (divn_val[i] != -1) {  in configure_main_pll()
141 		pllctl_reg_setbits(data->pll, alnctl, alnctl_val);  in configure_main_pll()
146 		pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);  in configure_main_pll()
150 	/* Reset PLL */  in configure_main_pll()
151 	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);  in configure_main_pll()
153 	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);  in configure_main_pll()
154 	sdelay(105000);	/* Wait for PLL Lock time (min 50 us) */  in configure_main_pll()
156 	/* Enable PLL */  in configure_main_pll()
157 	pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);  in configure_main_pll()
158 	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);  in configure_main_pll()
163 	int pllod = data->pll_od - 1;  in configure_secondary_pll()
165 	/* Enable Glitch free bypass for ARM PLL */  in configure_secondary_pll()
166 	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)  in configure_secondary_pll()
170 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);  in configure_secondary_pll()
171 	setbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
177 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
182 	/* Reset PLL */  in configure_secondary_pll()
183 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);  in configure_secondary_pll()
187 	/* Select the Output of PASS PLL as input to PASS */  in configure_secondary_pll()
188 	if (data->pll == PASS_PLL && cpu_is_k2hk())  in configure_secondary_pll()
191 	clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);  in configure_secondary_pll()
192 	/* Wait for 500 * REFCLK cucles * (PLLD + 1) */  in configure_secondary_pll()
195 	/* Switch to PLL mode */  in configure_secondary_pll()
196 	clrbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
199 	/* Select the Output of ARM PLL as input to ARM */  in configure_secondary_pll()
200 	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)  in configure_secondary_pll()
206 	if (data->pll == MAIN_PLL)  in init_pll()
221 	int pll;  in init_plls()  local
223 	for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {  in init_plls()
224 		data = get_pll_init_data(pll);  in init_plls()
235 	for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {  in get_max_speed()
249 	if (cpu_is_k2hk() && (cpu_revision() <= 1))  in read_efuse_bootrom()
276  * pll_freq_get - get pll frequency
277  * @pll:	pll identifier
279 static unsigned long pll_freq_get(int pll)  in pll_freq_get()  argument
281 	unsigned long mult = 1, prediv = 1, output_div = 2;  in pll_freq_get()
285 	if (pll == MAIN_PLL) {  in pll_freq_get()
287 		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {  in pll_freq_get()
288 			/* PLL mode */  in pll_freq_get()
290 			prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;  in pll_freq_get()
293 				(pllctl_reg_read(pll, mult) &  in pll_freq_get()
294 				 PLLM_MULT_LO_MASK)) + 1;  in pll_freq_get()
295 			output_div = ((pllctl_reg_read(pll, secctl) &  in pll_freq_get()
297 				       SECCTL_OP_DIV_SHIFT) + 1;  in pll_freq_get()
302 		switch (pll) {  in pll_freq_get()
331 			prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;  in pll_freq_get()
333 				CFG_PLLCTL0_PLLM_SHIFT) + 1;  in pll_freq_get()
335 				      CFG_PLLCTL0_CLKOD_SHIFT) + 1;  in pll_freq_get()
371 		freq = pll_freq_get(CORE_PLL) / pll0div_read(1);  in ks_clk_get_rate()