mach-imx/mx7/soc.c

1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/imx-regs.h>
11 #include <asm/mach-imx/dma.h>
12 #include <asm/mach-imx/hab.h>
13 #include <asm/mach-imx/rdc-sema.h>
14 #include <asm/arch/imx-rdc.h>
70  * at A7 core side. At default, all resources are in domain 0 - 3.
134 	struct fuse_bank *bank = &ocotp->bank[1];  in is_mx7d()
136 		(struct fuse_bank1_regs *)bank->fuse_regs;  in is_mx7d()
139 	val = readl(&fuse->tester4);  in is_mx7d()
150 	u32 reg = readl(&ccm_anatop->digprog);  in get_cpu_rev()
182 	 * The management data input/output (MDIO) requires open-drain,  in imx_enet_mdio_fixup()
189 		setbits_le32(&gpr_regs->gpr[0],  in imx_enet_mdio_fixup()
199 	 * Force IOMUXC irq pending, so that the interrupt to GPC can be  in imx_gpcv2_init()
296 		env_set("soc", "imx7d");  in arch_misc_init()
318  * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
322  * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
324  * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
329  * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
334 	struct fuse_bank *bank = &ocotp->bank[0];  in get_board_serial()
336 		(struct fuse_bank0_regs *)bank->fuse_regs;  in get_board_serial()
338 	serialnr->low = fuse->tester0;  in get_board_serial()
339 	serialnr->high = fuse->tester1;  in get_board_serial()
345 	u32 reg = readw(&wdog->wcr);  in set_wdog_reset()
351 	reg = readw(&wdog->wcr);  in set_wdog_reset()
354 	 * WDZST bit is write-once only bit. Align this bit in kernel,  in set_wdog_reset()
358 	writew(reg, &wdog->wcr);  in set_wdog_reset()