Lines Matching refs:clock_set_target_val

89 		clock_set_target_val(USB_HSIC_CLK_ROOT, target);  in enable_usboh3_clk()
540 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target); in enable_i2c_clk()
564 clock_set_target_val(USDHC1_CLK_ROOT, target); in init_clk_esdhc()
569 clock_set_target_val(USDHC2_CLK_ROOT, target); in init_clk_esdhc()
574 clock_set_target_val(USDHC3_CLK_ROOT, target); in init_clk_esdhc()
599 clock_set_target_val(UART1_CLK_ROOT, target); in init_clk_uart()
604 clock_set_target_val(UART2_CLK_ROOT, target); in init_clk_uart()
609 clock_set_target_val(UART3_CLK_ROOT, target); in init_clk_uart()
614 clock_set_target_val(UART4_CLK_ROOT, target); in init_clk_uart()
619 clock_set_target_val(UART5_CLK_ROOT, target); in init_clk_uart()
624 clock_set_target_val(UART6_CLK_ROOT, target); in init_clk_uart()
629 clock_set_target_val(UART7_CLK_ROOT, target); in init_clk_uart()
652 clock_set_target_val(EIM_CLK_ROOT, target); in init_clk_weim()
672 clock_set_target_val(ECSPI1_CLK_ROOT, target); in init_clk_ecspi()
677 clock_set_target_val(ECSPI2_CLK_ROOT, target); in init_clk_ecspi()
682 clock_set_target_val(ECSPI3_CLK_ROOT, target); in init_clk_ecspi()
687 clock_set_target_val(ECSPI4_CLK_ROOT, target); in init_clk_ecspi()
710 clock_set_target_val(WDOG_CLK_ROOT, target); in init_clk_wdog()
731 clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target); in init_clk_epdc()
863 clock_set_target_val(QSPI_CLK_ROOT, target); in set_clk_qspi()
883 clock_set_target_val(NAND_CLK_ROOT, target); in set_clk_nand()
951 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target); in mxs_set_lcdclk()
992 clock_set_target_val(ENET_AXI_CLK_ROOT, target); in set_clk_enet()
997 clock_set_target_val(ENET1_REF_CLK_ROOT, target); in set_clk_enet()
1002 clock_set_target_val(ENET1_TIME_CLK_ROOT, target); in set_clk_enet()
1007 clock_set_target_val(ENET2_REF_CLK_ROOT, target); in set_clk_enet()
1012 clock_set_target_val(ENET2_TIME_CLK_ROOT, target); in set_clk_enet()
1019 clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target); in set_clk_enet()