131 	debug("Starting write leveling calibration.\n");  in mmdc_do_write_level_calibration()
177 	debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);  in mmdc_do_write_level_calibration()
185 …debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. …  in mmdc_do_write_level_calibration()
217 	debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",  in mmdc_do_write_level_calibration()
219 	debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",  in mmdc_do_write_level_calibration()
222 		debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",  in mmdc_do_write_level_calibration()
224 		debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",  in mmdc_do_write_level_calibration()
356 	debug("Starting Read DQS Gating calibration.\n");  in mmdc_do_dqs_calibration()
418 	debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);  in mmdc_do_dqs_calibration()
425 	debug("Starting Read Delay calibration.\n");  in mmdc_do_dqs_calibration()
459 	debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);  in mmdc_do_dqs_calibration()
466 	debug("Starting Write Delay calibration.\n");  in mmdc_do_dqs_calibration()
513 	debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);  in mmdc_do_dqs_calibration()
558 	debug("MMDC registers updated from calibration\n");  in mmdc_do_dqs_calibration()
559 	debug("Read DQS gating calibration:\n");  in mmdc_do_dqs_calibration()
560 	debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));  in mmdc_do_dqs_calibration()
561 	debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));  in mmdc_do_dqs_calibration()
563 		debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));  in mmdc_do_dqs_calibration()
564 		debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));  in mmdc_do_dqs_calibration()
566 	debug("Read calibration:\n");  in mmdc_do_dqs_calibration()
567 	debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));  in mmdc_do_dqs_calibration()
569 		debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));  in mmdc_do_dqs_calibration()
570 	debug("Write calibration:\n");  in mmdc_do_dqs_calibration()
571 	debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));  in mmdc_do_dqs_calibration()
573 		debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));  in mmdc_do_dqs_calibration()
580 	debug("Status registers bounds for read DQS gating:\n");  in mmdc_do_dqs_calibration()
581 	debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));  in mmdc_do_dqs_calibration()
582 	debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));  in mmdc_do_dqs_calibration()
583 	debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));  in mmdc_do_dqs_calibration()
584 	debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));  in mmdc_do_dqs_calibration()
586 		debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));  in mmdc_do_dqs_calibration()
587 		debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));  in mmdc_do_dqs_calibration()
588 		debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));  in mmdc_do_dqs_calibration()
589 		debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));  in mmdc_do_dqs_calibration()
592 	debug("Final do_dqs_calibration error mask: 0x%x\n", errors);  in mmdc_do_dqs_calibration()
1072 	debug("density:%d Gb (%d Gb per chip)\n",  in mx6_lpddr2_cfg()
1074 	debug("clock: %dMHz (%d ps)\n", clock, clkper);  in mx6_lpddr2_cfg()
1075 	debug("memspd:%d\n", lpddr2_cfg->mem_speed);  in mx6_lpddr2_cfg()
1076 	debug("trcd_lp=%d\n", trcd_lp);  in mx6_lpddr2_cfg()
1077 	debug("trppb_lp=%d\n", trppb_lp);  in mx6_lpddr2_cfg()
1078 	debug("trpab_lp=%d\n", trpab_lp);  in mx6_lpddr2_cfg()
1079 	debug("trc_lp=%d\n", trc_lp);  in mx6_lpddr2_cfg()
1080 	debug("tcke=%d\n", tcke);  in mx6_lpddr2_cfg()
1081 	debug("tcksrx=%d\n", tcksrx);  in mx6_lpddr2_cfg()
1082 	debug("tcksre=%d\n", tcksre);  in mx6_lpddr2_cfg()
1083 	debug("trfc=%d\n", trfc);  in mx6_lpddr2_cfg()
1084 	debug("txsr=%d\n", txsr);  in mx6_lpddr2_cfg()
1085 	debug("txp=%d\n", txp);  in mx6_lpddr2_cfg()
1086 	debug("tfaw=%d\n", tfaw);  in mx6_lpddr2_cfg()
1087 	debug("tcl=%d\n", tcl);  in mx6_lpddr2_cfg()
1088 	debug("tras=%d\n", tras);  in mx6_lpddr2_cfg()
1089 	debug("twr=%d\n", twr);  in mx6_lpddr2_cfg()
1090 	debug("tmrd=%d\n", tmrd);  in mx6_lpddr2_cfg()
1091 	debug("twl=%d\n", twl);  in mx6_lpddr2_cfg()
1092 	debug("trtp=%d\n", trtp);  in mx6_lpddr2_cfg()
1093 	debug("twtr=%d\n", twtr);  in mx6_lpddr2_cfg()
1094 	debug("trrd=%d\n", trrd);  in mx6_lpddr2_cfg()
1095 	debug("cs0_end=%d\n", cs0_end);  in mx6_lpddr2_cfg()
1096 	debug("ncs=%d\n", sysinfo->ncs);  in mx6_lpddr2_cfg()
1343 	debug("density:%d Gb (%d Gb per chip)\n",  in mx6_ddr3_cfg()
1345 	debug("clock: %dMHz (%d ps)\n", clock, clkper);  in mx6_ddr3_cfg()
1346 	debug("memspd:%d\n", mem_speed);  in mx6_ddr3_cfg()
1347 	debug("tcke=%d\n", tcke);  in mx6_ddr3_cfg()
1348 	debug("tcksrx=%d\n", tcksrx);  in mx6_ddr3_cfg()
1349 	debug("tcksre=%d\n", tcksre);  in mx6_ddr3_cfg()
1350 	debug("taofpd=%d\n", taofpd);  in mx6_ddr3_cfg()
1351 	debug("taonpd=%d\n", taonpd);  in mx6_ddr3_cfg()
1352 	debug("todtlon=%d\n", todtlon);  in mx6_ddr3_cfg()
1353 	debug("tanpd=%d\n", tanpd);  in mx6_ddr3_cfg()
1354 	debug("taxpd=%d\n", taxpd);  in mx6_ddr3_cfg()
1355 	debug("trfc=%d\n", trfc);  in mx6_ddr3_cfg()
1356 	debug("txs=%d\n", txs);  in mx6_ddr3_cfg()
1357 	debug("txp=%d\n", txp);  in mx6_ddr3_cfg()
1358 	debug("txpdll=%d\n", txpdll);  in mx6_ddr3_cfg()
1359 	debug("tfaw=%d\n", tfaw);  in mx6_ddr3_cfg()
1360 	debug("tcl=%d\n", tcl);  in mx6_ddr3_cfg()
1361 	debug("trcd=%d\n", trcd);  in mx6_ddr3_cfg()
1362 	debug("trp=%d\n", trp);  in mx6_ddr3_cfg()
1363 	debug("trc=%d\n", trc);  in mx6_ddr3_cfg()
1364 	debug("tras=%d\n", tras);  in mx6_ddr3_cfg()
1365 	debug("twr=%d\n", twr);  in mx6_ddr3_cfg()
1366 	debug("tmrd=%d\n", tmrd);  in mx6_ddr3_cfg()
1367 	debug("tcwl=%d\n", tcwl);  in mx6_ddr3_cfg()
1368 	debug("tdllk=%d\n", tdllk);  in mx6_ddr3_cfg()
1369 	debug("trtp=%d\n", trtp);  in mx6_ddr3_cfg()
1370 	debug("twtr=%d\n", twtr);  in mx6_ddr3_cfg()
1371 	debug("trrd=%d\n", trrd);  in mx6_ddr3_cfg()
1372 	debug("txpr=%d\n", txpr);  in mx6_ddr3_cfg()
1373 	debug("cs0_end=%d\n", cs0_end);  in mx6_ddr3_cfg()
1374 	debug("ncs=%d\n", sysinfo->ncs);  in mx6_ddr3_cfg()
1375 	debug("Rtt_wr=%d\n", sysinfo->rtt_wr);  in mx6_ddr3_cfg()
1376 	debug("Rtt_nom=%d\n", sysinfo->rtt_nom);  in mx6_ddr3_cfg()
1377 	debug("SRT=%d\n", ddr3_cfg->SRT);  in mx6_ddr3_cfg()
1378 	debug("twr=%d\n", twr);  in mx6_ddr3_cfg()
1477 		debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));  in mx6_ddr3_cfg()
1480 		debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));  in mx6_ddr3_cfg()
1485 		debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));  in mx6_ddr3_cfg()
1492 		debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));  in mx6_ddr3_cfg()