mach-imx/mx6/ddr.c

916  *  - ddr3/lpddr2 chip details
923  * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
939  * According JESD209-2B-LPDDR2: Table 103
965  * According JESD209-2B-LPDDR2: Table 103
1019 	/* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */  in mx6_lpddr2_cfg()
1039 	 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,  in mx6_lpddr2_cfg()
1049 	/* tckesr for LPDDR2 */  in mx6_lpddr2_cfg()
1059 	/* LPDDR2 mode use tRCD_LP filed in MDCFG3. */  in mx6_lpddr2_cfg()
1065 	/* To LPDDR2, CL in MDCFG0 refers to RL */  in mx6_lpddr2_cfg()
1127 	 * In LPDDR2 mode this register should be cleared,  in mx6_lpddr2_cfg()
1167 			(0 << 19) |	/* Burst Length = 4 for LPDDR2 */  in mx6_lpddr2_cfg()
1178 	/* Step 8: Write Mode Registers to Init LPDDR2 devices */  in mx6_lpddr2_cfg()