Lines Matching +full:calibration +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/mx6-ddr.h>
21 /* Reset data FIFOs twice. */ in reset_read_data_fifos()
22 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); in reset_read_data_fifos()
23 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
25 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); in reset_read_data_fifos()
26 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
34 * Issue the Precharge-All command to the DDR device for both in precharge_all()
40 writel(0x04008050, &mmdc0->mdscr); in precharge_all()
41 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
45 writel(0x04008058, &mmdc0->mdscr); in precharge_all()
46 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
55 writel(0x800, &mmdc0->mpmur0); in force_delay_measurement()
57 writel(0x800, &mmdc1->mpmur0); in force_delay_measurement()
66 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80) in modify_dg_result()
72 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0; in modify_dg_result()
78 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0; in modify_dg_result()
115 * Stash old values in case calibration fails, in mmdc_do_write_level_calibration()
118 ldectrl[0] = readl(&mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
119 ldectrl[1] = readl(&mmdc0->mpwldectrl1); in mmdc_do_write_level_calibration()
120 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
121 ldectrl[2] = readl(&mmdc1->mpwldectrl0); in mmdc_do_write_level_calibration()
122 ldectrl[3] = readl(&mmdc1->mpwldectrl1); in mmdc_do_write_level_calibration()
126 clrbits_le32(&mmdc0->mdpdc, 0xff00); in mmdc_do_write_level_calibration()
129 setbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_write_level_calibration()
131 debug("Starting write leveling calibration.\n"); in mmdc_do_write_level_calibration()
134 * 2. disable auto refresh and ZQ calibration in mmdc_do_write_level_calibration()
135 * before proceeding with Write Leveling calibration in mmdc_do_write_level_calibration()
137 esdmisc_val = readl(&mmdc0->mdref); in mmdc_do_write_level_calibration()
138 writel(0x0000C000, &mmdc0->mdref); in mmdc_do_write_level_calibration()
139 zq_val = readl(&mmdc0->mpzqhwctrl); in mmdc_do_write_level_calibration()
140 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl); in mmdc_do_write_level_calibration()
144 setbits_le32(&mmdc0->mdmisc, rwalat_max); in mmdc_do_write_level_calibration()
145 if (sysinfo->dsize == 2) in mmdc_do_write_level_calibration()
146 setbits_le32(&mmdc1->mdmisc, rwalat_max); in mmdc_do_write_level_calibration()
148 * 4 & 5. Configure the external DDR device to enter write-leveling in mmdc_do_write_level_calibration()
156 writel(0x00808231, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
158 /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */ in mmdc_do_write_level_calibration()
159 writel(0x00000001, &mmdc0->mpwlgcr); in mmdc_do_write_level_calibration()
162 * 7. Upon completion of this process the MMDC de-asserts in mmdc_do_write_level_calibration()
165 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0); in mmdc_do_write_level_calibration()
171 if (readl(&mmdc0->mpwlgcr) & 0x00000F00) in mmdc_do_write_level_calibration()
173 if (sysinfo->dsize == 2) in mmdc_do_write_level_calibration()
174 if (readl(&mmdc1->mpwlgcr) & 0x00000F00) in mmdc_do_write_level_calibration()
177 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors); in mmdc_do_write_level_calibration()
180 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) && in mmdc_do_write_level_calibration()
181 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) && in mmdc_do_write_level_calibration()
182 ((sysinfo->dsize < 2) || in mmdc_do_write_level_calibration()
183 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) && in mmdc_do_write_level_calibration()
184 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) { in mmdc_do_write_level_calibration()
185 …debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. … in mmdc_do_write_level_calibration()
186 writel(ldectrl[0], &mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
187 writel(ldectrl[1], &mmdc0->mpwldectrl1); in mmdc_do_write_level_calibration()
188 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
189 writel(ldectrl[2], &mmdc1->mpwldectrl0); in mmdc_do_write_level_calibration()
190 writel(ldectrl[3], &mmdc1->mpwldectrl1); in mmdc_do_write_level_calibration()
195 correct_mpwldectr_result(&mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
196 correct_mpwldectr_result(&mmdc0->mpwldectrl1); in mmdc_do_write_level_calibration()
197 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
198 correct_mpwldectr_result(&mmdc1->mpwldectrl0); in mmdc_do_write_level_calibration()
199 correct_mpwldectr_result(&mmdc1->mpwldectrl1); in mmdc_do_write_level_calibration()
211 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
213 /* re-enable auto refresh and zq cal */ in mmdc_do_write_level_calibration()
214 writel(esdmisc_val, &mmdc0->mdref); in mmdc_do_write_level_calibration()
215 writel(zq_val, &mmdc0->mpzqhwctrl); in mmdc_do_write_level_calibration()
218 readl(&mmdc0->mpwldectrl0)); in mmdc_do_write_level_calibration()
220 readl(&mmdc0->mpwldectrl1)); in mmdc_do_write_level_calibration()
221 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
223 readl(&mmdc1->mpwldectrl0)); in mmdc_do_write_level_calibration()
225 readl(&mmdc1->mpwldectrl1)); in mmdc_do_write_level_calibration()
229 readl(&mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
230 readl(&mmdc0->mpwldectrl1); in mmdc_do_write_level_calibration()
231 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
232 readl(&mmdc1->mpwldectrl0); in mmdc_do_write_level_calibration()
233 readl(&mmdc1->mpwldectrl1); in mmdc_do_write_level_calibration()
237 setbits_le32(&mmdc0->mdpdc, 0x00005500); in mmdc_do_write_level_calibration()
240 clrbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_write_level_calibration()
243 writel(0, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
265 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
266 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
269 clrbits_le32(&mmdc0->mdpdc, 0xff00); in mmdc_do_dqs_calibration()
272 setbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_dqs_calibration()
275 setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000); in mmdc_do_dqs_calibration()
276 setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000); in mmdc_do_dqs_calibration()
277 setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000); in mmdc_do_dqs_calibration()
278 setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000); in mmdc_do_dqs_calibration()
279 setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000); in mmdc_do_dqs_calibration()
280 setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000); in mmdc_do_dqs_calibration()
281 setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000); in mmdc_do_dqs_calibration()
282 setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000); in mmdc_do_dqs_calibration()
285 esdmisc_val = readl(&mmdc0->mdmisc); in mmdc_do_dqs_calibration()
287 setbits_le32(&mmdc0->mdmisc, in mmdc_do_dqs_calibration()
290 /* Disable auto refresh before proceeding with calibration */ in mmdc_do_dqs_calibration()
291 temp_ref = readl(&mmdc0->mdref); in mmdc_do_dqs_calibration()
292 writel(0x0000c000, &mmdc0->mdref); in mmdc_do_dqs_calibration()
299 writel(0x00008020, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
301 writel(0x00008028, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
304 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in mmdc_do_dqs_calibration()
307 * Check MDMISC register CALIB_PER_CS to see which CS calibration in mmdc_do_dqs_calibration()
309 * as this is the default value, indicating calibration is directed in mmdc_do_dqs_calibration()
311 * Disable the other chip select not being target for calibration in mmdc_do_dqs_calibration()
312 * to avoid any potential issues. This will get re-enabled at end in mmdc_do_dqs_calibration()
313 * of calibration. in mmdc_do_dqs_calibration()
315 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0) in mmdc_do_dqs_calibration()
316 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */ in mmdc_do_dqs_calibration()
318 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */ in mmdc_do_dqs_calibration()
322 * the remainder of the calibration. in mmdc_do_dqs_calibration()
324 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
325 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
329 /* Write the pre-defined value into MPPDCMPR1 */ in mmdc_do_dqs_calibration()
330 writel(pddword, &mmdc0->mppdcmpr1); in mmdc_do_dqs_calibration()
337 setbits_le32(&mmdc0->mpswdar0, 1); in mmdc_do_dqs_calibration()
338 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0); in mmdc_do_dqs_calibration()
341 * (will be calibrated later in the read delay-line calibration). in mmdc_do_dqs_calibration()
344 writel(initdelay, &mmdc0->mprddlctl); in mmdc_do_dqs_calibration()
345 if (sysinfo->dsize == 0x2) in mmdc_do_dqs_calibration()
346 writel(initdelay, &mmdc1->mprddlctl); in mmdc_do_dqs_calibration()
349 force_delay_measurement(sysinfo->dsize); in mmdc_do_dqs_calibration()
353 * Read DQS Gating calibration in mmdc_do_dqs_calibration()
356 debug("Starting Read DQS Gating calibration.\n"); in mmdc_do_dqs_calibration()
359 * Reset the read data FIFOs (two resets); only need to issue reset in mmdc_do_dqs_calibration()
365 * Start the automatic read DQS gating calibration process by in mmdc_do_dqs_calibration()
370 * no errors were seen during calibration. in mmdc_do_dqs_calibration()
375 * 16 before comparing read data. in mmdc_do_dqs_calibration()
377 setbits_le32(&mmdc0->mpdgctrl0, 1 << 30); in mmdc_do_dqs_calibration()
378 if (sysinfo->dsize == 2) in mmdc_do_dqs_calibration()
379 setbits_le32(&mmdc1->mpdgctrl0, 1 << 30); in mmdc_do_dqs_calibration()
381 /* Set bit 28 to start automatic read DQS gating calibration */ in mmdc_do_dqs_calibration()
382 setbits_le32(&mmdc0->mpdgctrl0, 5 << 28); in mmdc_do_dqs_calibration()
385 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0); in mmdc_do_dqs_calibration()
388 * Check to see if any errors were encountered during calibration in mmdc_do_dqs_calibration()
392 if (readl(&mmdc0->mpdgctrl0) & 0x00001000) in mmdc_do_dqs_calibration()
395 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000)) in mmdc_do_dqs_calibration()
399 clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30); in mmdc_do_dqs_calibration()
400 if (sysinfo->dsize == 2) in mmdc_do_dqs_calibration()
401 clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30); in mmdc_do_dqs_calibration()
406 * reflecting (HW_DG_UPx - 0x80) in mmdc_do_dqs_calibration()
408 modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1, in mmdc_do_dqs_calibration()
409 &mmdc0->mpdgctrl0); in mmdc_do_dqs_calibration()
410 modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3, in mmdc_do_dqs_calibration()
411 &mmdc0->mpdgctrl1); in mmdc_do_dqs_calibration()
412 if (sysinfo->dsize == 0x2) { in mmdc_do_dqs_calibration()
413 modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1, in mmdc_do_dqs_calibration()
414 &mmdc1->mpdgctrl0); in mmdc_do_dqs_calibration()
415 modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3, in mmdc_do_dqs_calibration()
416 &mmdc1->mpdgctrl1); in mmdc_do_dqs_calibration()
418 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
422 * Read Delay calibration in mmdc_do_dqs_calibration()
425 debug("Starting Read Delay calibration.\n"); in mmdc_do_dqs_calibration()
430 * 4. Issue the Precharge-All command to the DDR device for both in mmdc_do_dqs_calibration()
437 * 9. Read delay-line calibration in mmdc_do_dqs_calibration()
438 * Start the automatic read calibration process by asserting in mmdc_do_dqs_calibration()
441 writel(0x00000030, &mmdc0->mprddlhwctl); in mmdc_do_dqs_calibration()
445 * MMDC indicates that the write data calibration had finished by in mmdc_do_dqs_calibration()
449 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0); in mmdc_do_dqs_calibration()
452 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f) in mmdc_do_dqs_calibration()
455 if ((sysinfo->dsize == 0x2) && in mmdc_do_dqs_calibration()
456 (readl(&mmdc1->mprddlhwctl) & 0x0000000f)) in mmdc_do_dqs_calibration()
459 debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
463 * Write Delay Calibration in mmdc_do_dqs_calibration()
466 debug("Starting Write Delay calibration.\n"); in mmdc_do_dqs_calibration()
471 * 4. Issue the Precharge-All command to the DDR device for both in mmdc_do_dqs_calibration()
481 writel(initdelay, &mmdc0->mpwrdlctl); in mmdc_do_dqs_calibration()
482 if (sysinfo->dsize == 0x2) in mmdc_do_dqs_calibration()
483 writel(initdelay, &mmdc1->mpwrdlctl); in mmdc_do_dqs_calibration()
489 force_delay_measurement(sysinfo->dsize); in mmdc_do_dqs_calibration()
492 * 9. 10. Start the automatic write calibration process in mmdc_do_dqs_calibration()
495 writel(0x00000030, &mmdc0->mpwrdlhwctl); in mmdc_do_dqs_calibration()
499 * MMDC indicates that the write data calibration had finished in mmdc_do_dqs_calibration()
503 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0); in mmdc_do_dqs_calibration()
506 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f) in mmdc_do_dqs_calibration()
509 if ((sysinfo->dsize == 0x2) && in mmdc_do_dqs_calibration()
510 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f)) in mmdc_do_dqs_calibration()
513 debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
518 setbits_le32(&mmdc0->mdpdc, 0x00005500); in mmdc_do_dqs_calibration()
521 clrbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_dqs_calibration()
524 writel(esdmisc_val, &mmdc0->mdmisc); in mmdc_do_dqs_calibration()
527 clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000); in mmdc_do_dqs_calibration()
528 clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000); in mmdc_do_dqs_calibration()
529 clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000); in mmdc_do_dqs_calibration()
530 clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000); in mmdc_do_dqs_calibration()
531 clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000); in mmdc_do_dqs_calibration()
532 clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000); in mmdc_do_dqs_calibration()
533 clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000); in mmdc_do_dqs_calibration()
534 clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000); in mmdc_do_dqs_calibration()
536 /* Re-enable SDE (chip selects) if they were set initially */ in mmdc_do_dqs_calibration()
539 setbits_le32(&mmdc0->mdctl, 1 << 30); in mmdc_do_dqs_calibration()
543 setbits_le32(&mmdc0->mdctl, 1 << 31); in mmdc_do_dqs_calibration()
545 /* Re-enable to auto refresh */ in mmdc_do_dqs_calibration()
546 writel(temp_ref, &mmdc0->mdref); in mmdc_do_dqs_calibration()
549 writel(0x0, &mmdc0->mdscr); /* CS0 */ in mmdc_do_dqs_calibration()
552 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0); in mmdc_do_dqs_calibration()
556 * of the calibration process. in mmdc_do_dqs_calibration()
558 debug("MMDC registers updated from calibration\n"); in mmdc_do_dqs_calibration()
559 debug("Read DQS gating calibration:\n"); in mmdc_do_dqs_calibration()
560 debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0)); in mmdc_do_dqs_calibration()
561 debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1)); in mmdc_do_dqs_calibration()
562 if (sysinfo->dsize == 2) { in mmdc_do_dqs_calibration()
563 debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0)); in mmdc_do_dqs_calibration()
564 debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1)); in mmdc_do_dqs_calibration()
566 debug("Read calibration:\n"); in mmdc_do_dqs_calibration()
567 debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl)); in mmdc_do_dqs_calibration()
568 if (sysinfo->dsize == 2) in mmdc_do_dqs_calibration()
569 debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl)); in mmdc_do_dqs_calibration()
570 debug("Write calibration:\n"); in mmdc_do_dqs_calibration()
571 debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl)); in mmdc_do_dqs_calibration()
572 if (sysinfo->dsize == 2) in mmdc_do_dqs_calibration()
573 debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl)); in mmdc_do_dqs_calibration()
578 * read DQS gating calibration. in mmdc_do_dqs_calibration()
581 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0)); in mmdc_do_dqs_calibration()
582 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1)); in mmdc_do_dqs_calibration()
583 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2)); in mmdc_do_dqs_calibration()
584 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3)); in mmdc_do_dqs_calibration()
585 if (sysinfo->dsize == 2) { in mmdc_do_dqs_calibration()
586 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0)); in mmdc_do_dqs_calibration()
587 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1)); in mmdc_do_dqs_calibration()
588 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2)); in mmdc_do_dqs_calibration()
589 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3)); in mmdc_do_dqs_calibration()
611 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type); in mx6sx_dram_iocfg()
612 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke); in mx6sx_dram_iocfg()
615 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0); in mx6sx_dram_iocfg()
618 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas); in mx6sx_dram_iocfg()
619 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras); in mx6sx_dram_iocfg()
620 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds); in mx6sx_dram_iocfg()
623 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset); in mx6sx_dram_iocfg()
624 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2); in mx6sx_dram_iocfg()
625 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0); in mx6sx_dram_iocfg()
626 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1); in mx6sx_dram_iocfg()
627 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0); in mx6sx_dram_iocfg()
628 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1); in mx6sx_dram_iocfg()
629 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds); in mx6sx_dram_iocfg()
631 /* Data Strobes */ in mx6sx_dram_iocfg()
632 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl); in mx6sx_dram_iocfg()
633 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0); in mx6sx_dram_iocfg()
634 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1); in mx6sx_dram_iocfg()
636 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2); in mx6sx_dram_iocfg()
637 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3); in mx6sx_dram_iocfg()
640 /* Data */ in mx6sx_dram_iocfg()
641 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode); in mx6sx_dram_iocfg()
642 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds); in mx6sx_dram_iocfg()
643 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds); in mx6sx_dram_iocfg()
645 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds); in mx6sx_dram_iocfg()
646 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds); in mx6sx_dram_iocfg()
648 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0); in mx6sx_dram_iocfg()
649 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1); in mx6sx_dram_iocfg()
651 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2); in mx6sx_dram_iocfg()
652 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3); in mx6sx_dram_iocfg()
669 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type); in mx6ul_dram_iocfg()
670 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke); in mx6ul_dram_iocfg()
673 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0); in mx6ul_dram_iocfg()
676 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas); in mx6ul_dram_iocfg()
677 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras); in mx6ul_dram_iocfg()
678 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds); in mx6ul_dram_iocfg()
681 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset); in mx6ul_dram_iocfg()
682 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2); in mx6ul_dram_iocfg()
683 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0); in mx6ul_dram_iocfg()
684 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1); in mx6ul_dram_iocfg()
685 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds); in mx6ul_dram_iocfg()
687 /* Data Strobes */ in mx6ul_dram_iocfg()
688 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl); in mx6ul_dram_iocfg()
689 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0); in mx6ul_dram_iocfg()
690 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1); in mx6ul_dram_iocfg()
692 /* Data */ in mx6ul_dram_iocfg()
693 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode); in mx6ul_dram_iocfg()
694 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds); in mx6ul_dram_iocfg()
695 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds); in mx6ul_dram_iocfg()
696 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0); in mx6ul_dram_iocfg()
697 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1); in mx6ul_dram_iocfg()
713 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; in mx6sl_dram_iocfg()
714 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; in mx6sl_dram_iocfg()
717 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; in mx6sl_dram_iocfg()
720 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6sl_dram_iocfg()
721 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6sl_dram_iocfg()
722 mx6_grp_iomux->grp_addds = grp->grp_addds; in mx6sl_dram_iocfg()
725 mx6_ddr_iomux->dram_reset = ddr->dram_reset; in mx6sl_dram_iocfg()
726 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; in mx6sl_dram_iocfg()
727 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; in mx6sl_dram_iocfg()
729 /* Data Strobes */ in mx6sl_dram_iocfg()
730 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; in mx6sl_dram_iocfg()
731 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; in mx6sl_dram_iocfg()
732 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; in mx6sl_dram_iocfg()
734 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; in mx6sl_dram_iocfg()
735 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; in mx6sl_dram_iocfg()
738 /* Data */ in mx6sl_dram_iocfg()
739 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; in mx6sl_dram_iocfg()
740 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6sl_dram_iocfg()
741 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; in mx6sl_dram_iocfg()
743 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; in mx6sl_dram_iocfg()
744 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; in mx6sl_dram_iocfg()
747 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6sl_dram_iocfg()
748 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6sl_dram_iocfg()
750 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; in mx6sl_dram_iocfg()
751 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; in mx6sl_dram_iocfg()
769 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; in mx6dq_dram_iocfg()
770 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; in mx6dq_dram_iocfg()
773 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; in mx6dq_dram_iocfg()
774 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; in mx6dq_dram_iocfg()
777 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6dq_dram_iocfg()
778 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6dq_dram_iocfg()
779 mx6_grp_iomux->grp_addds = grp->grp_addds; in mx6dq_dram_iocfg()
782 mx6_ddr_iomux->dram_reset = ddr->dram_reset; in mx6dq_dram_iocfg()
783 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; in mx6dq_dram_iocfg()
784 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; in mx6dq_dram_iocfg()
785 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; in mx6dq_dram_iocfg()
786 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; in mx6dq_dram_iocfg()
787 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; in mx6dq_dram_iocfg()
788 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; in mx6dq_dram_iocfg()
790 /* Data Strobes */ in mx6dq_dram_iocfg()
791 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; in mx6dq_dram_iocfg()
792 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; in mx6dq_dram_iocfg()
793 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; in mx6dq_dram_iocfg()
795 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; in mx6dq_dram_iocfg()
796 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; in mx6dq_dram_iocfg()
799 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; in mx6dq_dram_iocfg()
800 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; in mx6dq_dram_iocfg()
801 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; in mx6dq_dram_iocfg()
802 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; in mx6dq_dram_iocfg()
805 /* Data */ in mx6dq_dram_iocfg()
806 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; in mx6dq_dram_iocfg()
807 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6dq_dram_iocfg()
808 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; in mx6dq_dram_iocfg()
810 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; in mx6dq_dram_iocfg()
811 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; in mx6dq_dram_iocfg()
814 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; in mx6dq_dram_iocfg()
815 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; in mx6dq_dram_iocfg()
816 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; in mx6dq_dram_iocfg()
817 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; in mx6dq_dram_iocfg()
819 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6dq_dram_iocfg()
820 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6dq_dram_iocfg()
822 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; in mx6dq_dram_iocfg()
823 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; in mx6dq_dram_iocfg()
826 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; in mx6dq_dram_iocfg()
827 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; in mx6dq_dram_iocfg()
828 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; in mx6dq_dram_iocfg()
829 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; in mx6dq_dram_iocfg()
847 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; in mx6sdl_dram_iocfg()
848 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; in mx6sdl_dram_iocfg()
851 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; in mx6sdl_dram_iocfg()
852 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; in mx6sdl_dram_iocfg()
855 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6sdl_dram_iocfg()
856 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6sdl_dram_iocfg()
857 mx6_grp_iomux->grp_addds = grp->grp_addds; in mx6sdl_dram_iocfg()
860 mx6_ddr_iomux->dram_reset = ddr->dram_reset; in mx6sdl_dram_iocfg()
861 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; in mx6sdl_dram_iocfg()
862 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; in mx6sdl_dram_iocfg()
863 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; in mx6sdl_dram_iocfg()
864 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; in mx6sdl_dram_iocfg()
865 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; in mx6sdl_dram_iocfg()
866 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; in mx6sdl_dram_iocfg()
868 /* Data Strobes */ in mx6sdl_dram_iocfg()
869 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; in mx6sdl_dram_iocfg()
870 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; in mx6sdl_dram_iocfg()
871 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; in mx6sdl_dram_iocfg()
873 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; in mx6sdl_dram_iocfg()
874 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; in mx6sdl_dram_iocfg()
877 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; in mx6sdl_dram_iocfg()
878 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; in mx6sdl_dram_iocfg()
879 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; in mx6sdl_dram_iocfg()
880 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; in mx6sdl_dram_iocfg()
883 /* Data */ in mx6sdl_dram_iocfg()
884 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; in mx6sdl_dram_iocfg()
885 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6sdl_dram_iocfg()
886 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; in mx6sdl_dram_iocfg()
888 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; in mx6sdl_dram_iocfg()
889 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; in mx6sdl_dram_iocfg()
892 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; in mx6sdl_dram_iocfg()
893 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; in mx6sdl_dram_iocfg()
894 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; in mx6sdl_dram_iocfg()
895 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; in mx6sdl_dram_iocfg()
897 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6sdl_dram_iocfg()
898 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6sdl_dram_iocfg()
900 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; in mx6sdl_dram_iocfg()
901 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; in mx6sdl_dram_iocfg()
904 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; in mx6sdl_dram_iocfg()
905 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; in mx6sdl_dram_iocfg()
906 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; in mx6sdl_dram_iocfg()
907 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; in mx6sdl_dram_iocfg()
914 * - board-specific memory configuration
915 * - board-specific calibration data
916 * - ddr3/lpddr2 chip details
919 * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
935 mmdc1->entry = value; \
939 * According JESD209-2B-LPDDR2: Table 103
965 * According JESD209-2B-LPDDR2: Table 103
1009 if (sysinfo->dsize > 1) in mx6_lpddr2_cfg()
1017 twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1; in mx6_lpddr2_cfg()
1019 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */ in mx6_lpddr2_cfg()
1020 switch (lpddr2_cfg->density) { in mx6_lpddr2_cfg()
1024 trfc = DIV_ROUND_UP(130000, clkper) - 1; in mx6_lpddr2_cfg()
1025 txsr = DIV_ROUND_UP(140000, clkper) - 1; in mx6_lpddr2_cfg()
1028 trfc = DIV_ROUND_UP(210000, clkper) - 1; in mx6_lpddr2_cfg()
1029 txsr = DIV_ROUND_UP(220000, clkper) - 1; in mx6_lpddr2_cfg()
1041 txp = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1043 if (lpddr2_cfg->mem_speed == 333) in mx6_lpddr2_cfg()
1044 tfaw = DIV_ROUND_UP(60000, clkper) - 1; in mx6_lpddr2_cfg()
1046 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_lpddr2_cfg()
1047 trrd = DIV_ROUND_UP(10000, clkper) - 1; in mx6_lpddr2_cfg()
1052 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_lpddr2_cfg()
1058 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1; in mx6_lpddr2_cfg()
1060 trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1; in mx6_lpddr2_cfg()
1061 trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp, in mx6_lpddr2_cfg()
1062 clkper / 10) - 1; in mx6_lpddr2_cfg()
1063 trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1; in mx6_lpddr2_cfg()
1064 trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1; in mx6_lpddr2_cfg()
1066 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3; in mx6_lpddr2_cfg()
1067 twtr = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1068 trtp = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1070 cs0_end = 4 * sysinfo->cs_density - 1; in mx6_lpddr2_cfg()
1073 sysinfo->cs_density, lpddr2_cfg->density); in mx6_lpddr2_cfg()
1075 debug("memspd:%d\n", lpddr2_cfg->mem_speed); in mx6_lpddr2_cfg()
1096 debug("ncs=%d\n", sysinfo->ncs); in mx6_lpddr2_cfg()
1099 * board-specific configuration: in mx6_lpddr2_cfg()
1102 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; in mx6_lpddr2_cfg()
1103 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1; in mx6_lpddr2_cfg()
1104 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0; in mx6_lpddr2_cfg()
1105 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; in mx6_lpddr2_cfg()
1106 mmdc0->mprddlctl = calib->p0_mprddlctl; in mx6_lpddr2_cfg()
1107 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; in mx6_lpddr2_cfg()
1108 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl; in mx6_lpddr2_cfg()
1110 /* Read data DQ Byte0-3 delay */ in mx6_lpddr2_cfg()
1111 mmdc0->mprddqby0dl = 0x33333333; in mx6_lpddr2_cfg()
1112 mmdc0->mprddqby1dl = 0x33333333; in mx6_lpddr2_cfg()
1113 if (sysinfo->dsize > 0) { in mx6_lpddr2_cfg()
1114 mmdc0->mprddqby2dl = 0x33333333; in mx6_lpddr2_cfg()
1115 mmdc0->mprddqby3dl = 0x33333333; in mx6_lpddr2_cfg()
1118 /* Write data DQ Byte0-3 delay */ in mx6_lpddr2_cfg()
1119 mmdc0->mpwrdqby0dl = 0xf3333333; in mx6_lpddr2_cfg()
1120 mmdc0->mpwrdqby1dl = 0xf3333333; in mx6_lpddr2_cfg()
1121 if (sysinfo->dsize > 0) { in mx6_lpddr2_cfg()
1122 mmdc0->mpwrdqby2dl = 0xf3333333; in mx6_lpddr2_cfg()
1123 mmdc0->mpwrdqby3dl = 0xf3333333; in mx6_lpddr2_cfg()
1130 mmdc0->mpodtctrl = 0; in mx6_lpddr2_cfg()
1132 /* complete calibration */ in mx6_lpddr2_cfg()
1133 val = (1 << 11); /* Force measurement on delay-lines */ in mx6_lpddr2_cfg()
1134 mmdc0->mpmur0 = val; in mx6_lpddr2_cfg()
1137 mmdc0->mdscr = (u32)(1 << 15); /* config request */ in mx6_lpddr2_cfg()
1140 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) | in mx6_lpddr2_cfg()
1142 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl; in mx6_lpddr2_cfg()
1143 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd; in mx6_lpddr2_cfg()
1144 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) | in mx6_lpddr2_cfg()
1146 mmdc0->mdotc = 0; in mx6_lpddr2_cfg()
1148 mmdc0->mdasp = cs0_end; /* CS addressing */ in mx6_lpddr2_cfg()
1151 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) | in mx6_lpddr2_cfg()
1152 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) | in mx6_lpddr2_cfg()
1153 (sysinfo->ralat << 6) | (1 << 3); in mx6_lpddr2_cfg()
1156 mmdc0->mdor = (sysinfo->sde_to_rst << 8) | in mx6_lpddr2_cfg()
1157 (sysinfo->rst_to_cke << 0); in mx6_lpddr2_cfg()
1160 coladdr = lpddr2_cfg->coladdr; in mx6_lpddr2_cfg()
1161 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_lpddr2_cfg()
1163 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_lpddr2_cfg()
1165 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */ in mx6_lpddr2_cfg()
1166 (coladdr - 9) << 20 | /* COL */ in mx6_lpddr2_cfg()
1168 (sysinfo->dsize << 16); /* DDR data bus size */ in mx6_lpddr2_cfg()
1170 /* Step 6: Perform ZQ calibration */ in mx6_lpddr2_cfg()
1171 val = 0xa1390003; /* one-time HW ZQ calib */ in mx6_lpddr2_cfg()
1172 mmdc0->mpzqhwctrl = val; in mx6_lpddr2_cfg()
1175 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ in mx6_lpddr2_cfg()
1176 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ in mx6_lpddr2_cfg()
1179 for (cs = 0; cs < sysinfo->ncs; cs++) { in mx6_lpddr2_cfg()
1181 mmdc0->mdscr = MR(63, 0, 3, cs); in mx6_lpddr2_cfg()
1182 /* MR10: calibration, in mx6_lpddr2_cfg()
1183 * 0xff is calibration command after intilization. in mx6_lpddr2_cfg()
1186 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1189 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1192 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1195 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1198 /* Step 10: Power down control and self-refresh */ in mx6_lpddr2_cfg()
1199 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_lpddr2_cfg()
1205 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ in mx6_lpddr2_cfg()
1207 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ in mx6_lpddr2_cfg()
1209 mmdc0->mpzqhwctrl = val; in mx6_lpddr2_cfg()
1212 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); in mx6_lpddr2_cfg()
1214 /* Step 13: Deassert config request - init complete */ in mx6_lpddr2_cfg()
1215 mmdc0->mdscr = 0x00000000; in mx6_lpddr2_cfg()
1217 /* wait for auto-ZQ calibration to complete */ in mx6_lpddr2_cfg()
1238 u16 mem_speed = ddr3_cfg->mem_speed; in mx6_ddr3_cfg()
1261 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports in mx6_ddr3_cfg()
1274 switch (ddr3_cfg->density) { in mx6_ddr3_cfg()
1276 trfc = DIV_ROUND_UP(110000, clkper) - 1; in mx6_ddr3_cfg()
1277 txs = DIV_ROUND_UP(120000, clkper) - 1; in mx6_ddr3_cfg()
1280 trfc = DIV_ROUND_UP(160000, clkper) - 1; in mx6_ddr3_cfg()
1281 txs = DIV_ROUND_UP(170000, clkper) - 1; in mx6_ddr3_cfg()
1284 trfc = DIV_ROUND_UP(260000, clkper) - 1; in mx6_ddr3_cfg()
1285 txs = DIV_ROUND_UP(270000, clkper) - 1; in mx6_ddr3_cfg()
1288 trfc = DIV_ROUND_UP(350000, clkper) - 1; in mx6_ddr3_cfg()
1289 txs = DIV_ROUND_UP(360000, clkper) - 1; in mx6_ddr3_cfg()
1301 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1302 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1303 if (ddr3_cfg->pagesz == 1) { in mx6_ddr3_cfg()
1304 tfaw = DIV_ROUND_UP(40000, clkper) - 1; in mx6_ddr3_cfg()
1305 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1307 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
1308 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1312 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1313 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1; in mx6_ddr3_cfg()
1314 if (ddr3_cfg->pagesz == 1) { in mx6_ddr3_cfg()
1315 tfaw = DIV_ROUND_UP(37500, clkper) - 1; in mx6_ddr3_cfg()
1316 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1318 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
1319 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1327 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1; in mx6_ddr3_cfg()
1329 taonpd = DIV_ROUND_UP(2000, clkper) - 1; in mx6_ddr3_cfg()
1332 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_ddr3_cfg()
1333 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1; in mx6_ddr3_cfg()
1334 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1; in mx6_ddr3_cfg()
1335 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1; in mx6_ddr3_cfg()
1336 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3; in mx6_ddr3_cfg()
1337 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1; in mx6_ddr3_cfg()
1338 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1; in mx6_ddr3_cfg()
1341 cs0_end = 4 * sysinfo->cs_density - 1; in mx6_ddr3_cfg()
1344 sysinfo->cs_density, ddr3_cfg->density); in mx6_ddr3_cfg()
1374 debug("ncs=%d\n", sysinfo->ncs); in mx6_ddr3_cfg()
1375 debug("Rtt_wr=%d\n", sysinfo->rtt_wr); in mx6_ddr3_cfg()
1376 debug("Rtt_nom=%d\n", sysinfo->rtt_nom); in mx6_ddr3_cfg()
1377 debug("SRT=%d\n", ddr3_cfg->SRT); in mx6_ddr3_cfg()
1381 * board-specific configuration: in mx6_ddr3_cfg()
1386 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; in mx6_ddr3_cfg()
1387 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1; in mx6_ddr3_cfg()
1388 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0; in mx6_ddr3_cfg()
1389 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; in mx6_ddr3_cfg()
1390 mmdc0->mprddlctl = calib->p0_mprddlctl; in mx6_ddr3_cfg()
1391 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; in mx6_ddr3_cfg()
1392 if (sysinfo->dsize > 1) { in mx6_ddr3_cfg()
1393 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0); in mx6_ddr3_cfg()
1394 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1); in mx6_ddr3_cfg()
1395 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0); in mx6_ddr3_cfg()
1396 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1); in mx6_ddr3_cfg()
1397 MMDC1(mprddlctl, calib->p1_mprddlctl); in mx6_ddr3_cfg()
1398 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl); in mx6_ddr3_cfg()
1401 /* Read data DQ Byte0-3 delay */ in mx6_ddr3_cfg()
1402 mmdc0->mprddqby0dl = 0x33333333; in mx6_ddr3_cfg()
1403 mmdc0->mprddqby1dl = 0x33333333; in mx6_ddr3_cfg()
1404 if (sysinfo->dsize > 0) { in mx6_ddr3_cfg()
1405 mmdc0->mprddqby2dl = 0x33333333; in mx6_ddr3_cfg()
1406 mmdc0->mprddqby3dl = 0x33333333; in mx6_ddr3_cfg()
1409 if (sysinfo->dsize > 1) { in mx6_ddr3_cfg()
1417 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227; in mx6_ddr3_cfg()
1418 mmdc0->mpodtctrl = val; in mx6_ddr3_cfg()
1419 if (sysinfo->dsize > 1) in mx6_ddr3_cfg()
1422 /* complete calibration */ in mx6_ddr3_cfg()
1423 val = (1 << 11); /* Force measurement on delay-lines */ in mx6_ddr3_cfg()
1424 mmdc0->mpmur0 = val; in mx6_ddr3_cfg()
1425 if (sysinfo->dsize > 1) in mx6_ddr3_cfg()
1429 mmdc0->mdscr = (u32)(1 << 15); /* config request */ in mx6_ddr3_cfg()
1432 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) | in mx6_ddr3_cfg()
1434 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) | in mx6_ddr3_cfg()
1437 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; in mx6_ddr3_cfg()
1438 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | in mx6_ddr3_cfg()
1440 mmdc0->mdasp = cs0_end; /* CS addressing */ in mx6_ddr3_cfg()
1443 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) | in mx6_ddr3_cfg()
1444 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) | in mx6_ddr3_cfg()
1445 (sysinfo->ralat << 6); in mx6_ddr3_cfg()
1448 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) | in mx6_ddr3_cfg()
1449 (sysinfo->rst_to_cke << 0); in mx6_ddr3_cfg()
1452 coladdr = ddr3_cfg->coladdr; in mx6_ddr3_cfg()
1453 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_ddr3_cfg()
1455 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_ddr3_cfg()
1457 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */ in mx6_ddr3_cfg()
1458 (coladdr - 9) << 20 | /* COL */ in mx6_ddr3_cfg()
1460 (sysinfo->dsize << 16); /* DDR data bus size */ in mx6_ddr3_cfg()
1462 /* Step 6: Perform ZQ calibration */ in mx6_ddr3_cfg()
1463 val = 0xa1390001; /* one-time HW ZQ calib */ in mx6_ddr3_cfg()
1464 mmdc0->mpzqhwctrl = val; in mx6_ddr3_cfg()
1465 if (sysinfo->dsize > 1) in mx6_ddr3_cfg()
1469 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ in mx6_ddr3_cfg()
1470 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ in mx6_ddr3_cfg()
1473 for (cs = 0; cs < sysinfo->ncs; cs++) { in mx6_ddr3_cfg()
1475 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 | in mx6_ddr3_cfg()
1476 ((tcwl - 3) & 3) << 3; in mx6_ddr3_cfg()
1478 mmdc0->mdscr = MR(val, 2, 3, cs); in mx6_ddr3_cfg()
1481 mmdc0->mdscr = MR(0, 3, 3, cs); in mx6_ddr3_cfg()
1483 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 | in mx6_ddr3_cfg()
1484 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6; in mx6_ddr3_cfg()
1486 mmdc0->mdscr = MR(val, 1, 3, cs); in mx6_ddr3_cfg()
1488 val = ((tcl - 1) << 4) | /* CAS */ in mx6_ddr3_cfg()
1490 ((twr - 3) << 9) | /* Write Recovery */ in mx6_ddr3_cfg()
1491 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */ in mx6_ddr3_cfg()
1493 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_ddr3_cfg()
1494 /* ZQ calibration */ in mx6_ddr3_cfg()
1496 mmdc0->mdscr = MR(val, 0, 4, cs); in mx6_ddr3_cfg()
1499 /* Step 10: Power down control and self-refresh */ in mx6_ddr3_cfg()
1500 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_ddr3_cfg()
1506 if (!sysinfo->pd_fast_exit) in mx6_ddr3_cfg()
1507 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */ in mx6_ddr3_cfg()
1508 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ in mx6_ddr3_cfg()
1510 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ in mx6_ddr3_cfg()
1512 mmdc0->mpzqhwctrl = val; in mx6_ddr3_cfg()
1513 if (sysinfo->dsize > 1) in mx6_ddr3_cfg()
1517 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); in mx6_ddr3_cfg()
1519 /* Step 13: Deassert config request - init complete */ in mx6_ddr3_cfg()
1520 mmdc0->mdscr = 0x00000000; in mx6_ddr3_cfg()
1522 /* wait for auto-ZQ calibration to complete */ in mx6_ddr3_cfg()
1532 calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0); in mmdc_read_calibration()
1533 calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1); in mmdc_read_calibration()
1534 calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0); in mmdc_read_calibration()
1535 calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1); in mmdc_read_calibration()
1536 calib->p0_mprddlctl = readl(&mmdc0->mprddlctl); in mmdc_read_calibration()
1537 calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl); in mmdc_read_calibration()
1539 if (sysinfo->dsize == 2) { in mmdc_read_calibration()
1540 calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0); in mmdc_read_calibration()
1541 calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1); in mmdc_read_calibration()
1542 calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0); in mmdc_read_calibration()
1543 calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1); in mmdc_read_calibration()
1544 calib->p1_mprddlctl = readl(&mmdc1->mprddlctl); in mmdc_read_calibration()
1545 calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl); in mmdc_read_calibration()
1553 if (sysinfo->ddr_type == DDR_TYPE_DDR3) { in mx6_dram_cfg()
1555 } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) { in mx6_dram_cfg()