Lines Matching +full:0 +full:x7000
23 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
26 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
40 writel(0x04008050, &mmdc0->mdscr); in precharge_all()
41 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
45 writel(0x04008058, &mmdc0->mdscr); in precharge_all()
46 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
55 writel(0x800, &mmdc0->mpmur0); in force_delay_measurement()
56 if (bus_size == 0x2) in force_delay_measurement()
57 writel(0x800, &mmdc1->mpmur0); in force_delay_measurement()
66 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80) in modify_dg_result()
70 val_ctrl &= 0xf0000000; in modify_dg_result()
72 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0; in modify_dg_result()
73 dg_dl_abs_offset = dg_tmp_val & 0x7f; in modify_dg_result()
74 dg_hc_del = (dg_tmp_val & 0x780) << 1; in modify_dg_result()
78 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0; in modify_dg_result()
79 dg_dl_abs_offset = dg_tmp_val & 0x7f; in modify_dg_result()
80 dg_hc_del = (dg_tmp_val & 0x780) << 1; in modify_dg_result()
89 /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */ in correct_mpwldectr_result()
90 const unsigned int limit = 0x148; in correct_mpwldectr_result()
94 if ((val & 0x17f) > limit) in correct_mpwldectr_result()
95 val &= 0xffff << 16; in correct_mpwldectr_result()
97 if (((val >> 16) & 0x17f) > limit) in correct_mpwldectr_result()
98 val &= 0xffff; in correct_mpwldectr_result()
109 u32 errors = 0; in mmdc_do_write_level_calibration()
110 u32 ldectrl[4] = {0}; in mmdc_do_write_level_calibration()
111 u32 ddr_mr1 = 0x4; in mmdc_do_write_level_calibration()
118 ldectrl[0] = readl(&mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
126 clrbits_le32(&mmdc0->mdpdc, 0xff00); in mmdc_do_write_level_calibration()
129 setbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_write_level_calibration()
138 writel(0x0000C000, &mmdc0->mdref); in mmdc_do_write_level_calibration()
140 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl); in mmdc_do_write_level_calibration()
151 * Bits[31:16] MR1 value (0x0080 write leveling enable) in mmdc_do_write_level_calibration()
154 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming in mmdc_do_write_level_calibration()
156 writel(0x00808231, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
159 writel(0x00000001, &mmdc0->mpwlgcr); in mmdc_do_write_level_calibration()
165 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0); in mmdc_do_write_level_calibration()
171 if (readl(&mmdc0->mpwlgcr) & 0x00000F00) in mmdc_do_write_level_calibration()
174 if (readl(&mmdc1->mpwlgcr) & 0x00000F00) in mmdc_do_write_level_calibration()
177 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors); in mmdc_do_write_level_calibration()
180 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) && in mmdc_do_write_level_calibration()
181 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) && in mmdc_do_write_level_calibration()
183 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) && in mmdc_do_write_level_calibration()
184 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) { in mmdc_do_write_level_calibration()
186 writel(ldectrl[0], &mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
209 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming in mmdc_do_write_level_calibration()
211 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
217 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
219 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
222 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
224 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
237 setbits_le32(&mmdc0->mdpdc, 0x00005500); in mmdc_do_write_level_calibration()
240 clrbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_write_level_calibration()
243 writel(0, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
260 u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */ in mmdc_do_dqs_calibration()
261 u32 errors = 0; in mmdc_do_dqs_calibration()
262 u32 initdelay = 0x40404040; in mmdc_do_dqs_calibration()
265 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
266 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
269 clrbits_le32(&mmdc0->mdpdc, 0xff00); in mmdc_do_dqs_calibration()
272 setbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_dqs_calibration()
275 setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000); in mmdc_do_dqs_calibration()
276 setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000); in mmdc_do_dqs_calibration()
277 setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000); in mmdc_do_dqs_calibration()
278 setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000); in mmdc_do_dqs_calibration()
279 setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000); in mmdc_do_dqs_calibration()
280 setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000); in mmdc_do_dqs_calibration()
281 setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000); in mmdc_do_dqs_calibration()
282 setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000); in mmdc_do_dqs_calibration()
292 writel(0x0000c000, &mmdc0->mdref); in mmdc_do_dqs_calibration()
295 * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2, in mmdc_do_dqs_calibration()
299 writel(0x00008020, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
301 writel(0x00008028, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
304 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in mmdc_do_dqs_calibration()
315 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0) in mmdc_do_dqs_calibration()
324 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
325 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
334 * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll in mmdc_do_dqs_calibration()
338 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0); in mmdc_do_dqs_calibration()
345 if (sysinfo->dsize == 0x2) in mmdc_do_dqs_calibration()
384 /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */ in mmdc_do_dqs_calibration()
385 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0); in mmdc_do_dqs_calibration()
392 if (readl(&mmdc0->mpdgctrl0) & 0x00001000) in mmdc_do_dqs_calibration()
395 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000)) in mmdc_do_dqs_calibration()
406 * reflecting (HW_DG_UPx - 0x80) in mmdc_do_dqs_calibration()
412 if (sysinfo->dsize == 0x2) { in mmdc_do_dqs_calibration()
418 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
441 writel(0x00000030, &mmdc0->mprddlhwctl); in mmdc_do_dqs_calibration()
446 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that in mmdc_do_dqs_calibration()
449 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0); in mmdc_do_dqs_calibration()
452 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f) in mmdc_do_dqs_calibration()
455 if ((sysinfo->dsize == 0x2) && in mmdc_do_dqs_calibration()
456 (readl(&mmdc1->mprddlhwctl) & 0x0000000f)) in mmdc_do_dqs_calibration()
459 debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
482 if (sysinfo->dsize == 0x2) in mmdc_do_dqs_calibration()
495 writel(0x00000030, &mmdc0->mpwrdlhwctl); in mmdc_do_dqs_calibration()
500 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0. in mmdc_do_dqs_calibration()
503 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0); in mmdc_do_dqs_calibration()
506 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f) in mmdc_do_dqs_calibration()
509 if ((sysinfo->dsize == 0x2) && in mmdc_do_dqs_calibration()
510 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f)) in mmdc_do_dqs_calibration()
513 debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
518 setbits_le32(&mmdc0->mdpdc, 0x00005500); in mmdc_do_dqs_calibration()
521 clrbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_dqs_calibration()
527 clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000); in mmdc_do_dqs_calibration()
528 clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000); in mmdc_do_dqs_calibration()
529 clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000); in mmdc_do_dqs_calibration()
530 clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000); in mmdc_do_dqs_calibration()
531 clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000); in mmdc_do_dqs_calibration()
532 clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000); in mmdc_do_dqs_calibration()
533 clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000); in mmdc_do_dqs_calibration()
534 clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000); in mmdc_do_dqs_calibration()
549 writel(0x0, &mmdc0->mdscr); /* CS0 */ in mmdc_do_dqs_calibration()
552 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0); in mmdc_do_dqs_calibration()
560 debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0)); in mmdc_do_dqs_calibration()
561 debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1)); in mmdc_do_dqs_calibration()
563 debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0)); in mmdc_do_dqs_calibration()
564 debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1)); in mmdc_do_dqs_calibration()
567 debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl)); in mmdc_do_dqs_calibration()
569 debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl)); in mmdc_do_dqs_calibration()
571 debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl)); in mmdc_do_dqs_calibration()
573 debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl)); in mmdc_do_dqs_calibration()
581 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0)); in mmdc_do_dqs_calibration()
582 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1)); in mmdc_do_dqs_calibration()
583 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2)); in mmdc_do_dqs_calibration()
584 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3)); in mmdc_do_dqs_calibration()
586 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0)); in mmdc_do_dqs_calibration()
587 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1)); in mmdc_do_dqs_calibration()
588 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2)); in mmdc_do_dqs_calibration()
589 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3)); in mmdc_do_dqs_calibration()
592 debug("Final do_dqs_calibration error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
936 } while (0)
961 return 0; in lpddr2_wl()
989 return 0; in lpddr2_rl()
1040 * set them to 0. */ in mx6_lpddr2_cfg()
1111 mmdc0->mprddqby0dl = 0x33333333; in mx6_lpddr2_cfg()
1112 mmdc0->mprddqby1dl = 0x33333333; in mx6_lpddr2_cfg()
1113 if (sysinfo->dsize > 0) { in mx6_lpddr2_cfg()
1114 mmdc0->mprddqby2dl = 0x33333333; in mx6_lpddr2_cfg()
1115 mmdc0->mprddqby3dl = 0x33333333; in mx6_lpddr2_cfg()
1119 mmdc0->mpwrdqby0dl = 0xf3333333; in mx6_lpddr2_cfg()
1120 mmdc0->mpwrdqby1dl = 0xf3333333; in mx6_lpddr2_cfg()
1121 if (sysinfo->dsize > 0) { in mx6_lpddr2_cfg()
1122 mmdc0->mpwrdqby2dl = 0xf3333333; in mx6_lpddr2_cfg()
1123 mmdc0->mpwrdqby3dl = 0xf3333333; in mx6_lpddr2_cfg()
1130 mmdc0->mpodtctrl = 0; in mx6_lpddr2_cfg()
1146 mmdc0->mdotc = 0; in mx6_lpddr2_cfg()
1157 (sysinfo->rst_to_cke << 0); in mx6_lpddr2_cfg()
1161 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_lpddr2_cfg()
1163 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_lpddr2_cfg()
1167 (0 << 19) | /* Burst Length = 4 for LPDDR2 */ in mx6_lpddr2_cfg()
1171 val = 0xa1390003; /* one-time HW ZQ calib */ in mx6_lpddr2_cfg()
1176 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ in mx6_lpddr2_cfg()
1179 for (cs = 0; cs < sysinfo->ncs; cs++) { in mx6_lpddr2_cfg()
1181 mmdc0->mdscr = MR(63, 0, 3, cs); in mx6_lpddr2_cfg()
1183 * 0xff is calibration command after intilization. in mx6_lpddr2_cfg()
1185 val = 0xA | (0xff << 8); in mx6_lpddr2_cfg()
1186 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1188 val = 0x1 | (0x82 << 8); in mx6_lpddr2_cfg()
1189 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1191 val = 0x2 | (0x04 << 8); in mx6_lpddr2_cfg()
1192 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1194 val = 0x3 | (0x02 << 8); in mx6_lpddr2_cfg()
1195 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1199 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_lpddr2_cfg()
1203 (tcksrx & 0x7) << 3 | in mx6_lpddr2_cfg()
1204 (tcksre & 0x7); in mx6_lpddr2_cfg()
1205 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ in mx6_lpddr2_cfg()
1208 val = 0xa1310003; in mx6_lpddr2_cfg()
1215 mmdc0->mdscr = 0x00000000; in mx6_lpddr2_cfg()
1230 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ in mx6_ddr3_cfg()
1233 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ in mx6_ddr3_cfg()
1402 mmdc0->mprddqby0dl = 0x33333333; in mx6_ddr3_cfg()
1403 mmdc0->mprddqby1dl = 0x33333333; in mx6_ddr3_cfg()
1404 if (sysinfo->dsize > 0) { in mx6_ddr3_cfg()
1405 mmdc0->mprddqby2dl = 0x33333333; in mx6_ddr3_cfg()
1406 mmdc0->mprddqby3dl = 0x33333333; in mx6_ddr3_cfg()
1410 MMDC1(mprddqby0dl, 0x33333333); in mx6_ddr3_cfg()
1411 MMDC1(mprddqby1dl, 0x33333333); in mx6_ddr3_cfg()
1412 MMDC1(mprddqby2dl, 0x33333333); in mx6_ddr3_cfg()
1413 MMDC1(mprddqby3dl, 0x33333333); in mx6_ddr3_cfg()
1417 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227; in mx6_ddr3_cfg()
1449 (sysinfo->rst_to_cke << 0); in mx6_ddr3_cfg()
1453 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_ddr3_cfg()
1455 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_ddr3_cfg()
1463 val = 0xa1390001; /* one-time HW ZQ calib */ in mx6_ddr3_cfg()
1470 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ in mx6_ddr3_cfg()
1473 for (cs = 0; cs < sysinfo->ncs; cs++) { in mx6_ddr3_cfg()
1477 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs)); in mx6_ddr3_cfg()
1480 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs)); in mx6_ddr3_cfg()
1481 mmdc0->mdscr = MR(0, 3, 3, cs); in mx6_ddr3_cfg()
1483 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 | in mx6_ddr3_cfg()
1484 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6; in mx6_ddr3_cfg()
1485 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs)); in mx6_ddr3_cfg()
1492 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs)); in mx6_ddr3_cfg()
1493 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_ddr3_cfg()
1496 mmdc0->mdscr = MR(val, 0, 4, cs); in mx6_ddr3_cfg()
1500 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_ddr3_cfg()
1504 (tcksrx & 0x7) << 3 | in mx6_ddr3_cfg()
1505 (tcksre & 0x7); in mx6_ddr3_cfg()
1508 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ in mx6_ddr3_cfg()
1511 val = 0xa1390003; in mx6_ddr3_cfg()
1520 mmdc0->mdscr = 0x00000000; in mx6_ddr3_cfg()