Lines Matching refs:str

64 	str r1, [r0, #0x0]
65 	str r1, [r0, #0x4]
67 	str r1, [r0, #0x0]
68 	str r1, [r0, #0x4]
85 	str r1, [r0, #0x40]
87 	str r4, [r0, #0x44]
90 	str r1, [r0, #0x9C]
93 	str r1, [r0, #0x48]
110 	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
112 	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
115 	str r1, [r0, #PLL_DP_OP]
116 	str r1, [r0, #PLL_DP_HFS_OP]
119 	str r1, [r0, #PLL_DP_MFD]
120 	str r1, [r0, #PLL_DP_HFS_MFD]
123 	str r1, [r0, #PLL_DP_MFN]
124 	str r1, [r0, #PLL_DP_HFS_MFN]
127 	str r1, [r0, #PLL_DP_CTL]
137 	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
139 	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
145 	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
146 	str r5, [r2, #PLL_DP_HFS_MFN]
149 	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
160 	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
169 	str r1, [r0, #CLKCTL_CCGR0]
170 	str r4, [r0, #CLKCTL_CCGR1]
171 	str r4, [r0, #CLKCTL_CCGR2]
172 	str r4, [r0, #CLKCTL_CCGR3]
175 	str r1, [r0, #CLKCTL_CCGR4]
177 	str r1, [r0, #CLKCTL_CCGR5]
179 	str r1, [r0, #CLKCTL_CCGR6]
183 	str r1, [r0, #CLKCTL_CCDR]
187 	str r1, [r0, #CLKCTL_CBCDR]
195 	str r1, [r0, #CLKCTL_CCSR]
209 	str r1, [r0, #CLKCTL_CBCMR]
211 	str r1, [r0, #CLKCTL_CBCDR]
217 	str r1, [r0, #CLKCTL_CBCDR]
219 	str r1, [r0, #CLKCTL_CBCMR]
226 	str r1, [r0, #0x14]
236 	str r1, [r0, #CLKCTL_CACRR]
239 	str r4, [r0, #CLKCTL_CCSR]
244 	str r1, [r0, #CLKCTL_CBCMR]
247 	str r1, [r0, #CLKCTL_CBCDR]
251 	str r1, [r0, #CLKCTL_CCGR0]
252 	str r1, [r0, #CLKCTL_CCGR1]
253 	str r1, [r0, #CLKCTL_CCGR2]
254 	str r1, [r0, #CLKCTL_CCGR3]
255 	str r1, [r0, #CLKCTL_CCGR4]
256 	str r1, [r0, #CLKCTL_CCGR5]
257 	str r1, [r0, #CLKCTL_CCGR6]
261 	str r1, [r0, #CLKCTL_CSCMR1]
263 	str r1, [r0, #CLKCTL_CSCDR1]
269 	str r4, [r0, #CLKCTL_CCDR]
274 	str r1, [r0, #CLKCTL_CCOSR]
280 	str r1, [r0, #CLKCTL_CCGR0]
281 	str r4, [r0, #CLKCTL_CCGR1]
282 	str r4, [r0, #CLKCTL_CCGR2]
283 	str r4, [r0, #CLKCTL_CCGR3]
284 	str r4, [r0, #CLKCTL_CCGR7]
286 	str r1, [r0, #CLKCTL_CCGR4]
288 	str r1, [r0, #CLKCTL_CCGR5]
290 	str r1, [r0, #CLKCTL_CCGR6]
294 	str r1, [r0, #CLKCTL_CCSR]
303 	str r1, [r0, #CLKCTL_CBCMR]
305 	str r1, [r0, #CLKCTL_CBCDR]
316 	str r1, [r0, #CLKCTL_CBCDR]
319 	str r1, [r0, #CLKCTL_CBCMR]
325 	str r1, [r0, #CLKCTL_CSCMR1]
339 	str r1, [r0, #0x14]
343 	str r1, [r0, #CLKCTL_CACRR]
347 	str r1, [r0, #CLKCTL_CCSR]
353 	str r1, [r0, #CLKCTL_CSCDR1]
357 	str r1, [r0, #CLKCTL_CCGR0]
358 	str r1, [r0, #CLKCTL_CCGR1]
359 	str r1, [r0, #CLKCTL_CCGR2]
360 	str r1, [r0, #CLKCTL_CCGR3]
361 	str r1, [r0, #CLKCTL_CCGR4]
362 	str r1, [r0, #CLKCTL_CCGR5]
363 	str r1, [r0, #CLKCTL_CCGR6]
364 	str r1, [r0, #CLKCTL_CCGR7]
367 	str r1, [r0, #CLKCTL_CCDR]
372 	str r1, [r0, #CLKCTL_CCOSR]
385 	str r1, [r0, #0x0]
388 	str r1, [r0, #0x4]