254 	u32 reg, freq;  in get_mcu_main_clk()  local
257 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in get_mcu_main_clk()
258 	return freq / (reg + 1);  in get_mcu_main_clk()
290 	uint32_t freq, reg, div;  in get_ipg_clk()  local
292 	freq = get_ahb_clk();  in get_ipg_clk()
297 	return freq / div;  in get_ipg_clk()
305 	u32 freq, pred1, pred2, podf;  in get_ipg_per_clk()  local
311 		freq = get_lp_apm();  in get_ipg_per_clk()
313 		freq = get_periph_clk();  in get_ipg_per_clk()
318 	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));  in get_ipg_per_clk()
324 	u32 freq = 0;  in get_standard_pll_sel_clk()  local
328 		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
331 		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
334 		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
337 		freq = get_lp_apm();  in get_standard_pll_sel_clk()
341 	return freq;  in get_standard_pll_sel_clk()
349 	unsigned int clk_sel, freq, reg, pred, podf;  in get_uart_clk()  local
353 	freq = get_standard_pll_sel_clk(clk_sel);  in get_uart_clk()
358 	freq /= (pred + 1) * (podf + 1);  in get_uart_clk()
360 	return freq;  in get_uart_clk()
368 	u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;  in imx_get_cspiclk()  local
375 	freq = get_standard_pll_sel_clk(clk_sel);  in imx_get_cspiclk()
376 	ret_val = freq / ((pre_pdf + 1) * (pdf + 1));  in imx_get_cspiclk()
385 	u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;  in get_esdhc_clk()  local
414 	freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));  in get_esdhc_clk()
415 	return freq;  in get_esdhc_clk()
705 static int config_core_clk(u32 ref, u32 freq)  in config_core_clk()  argument
713 	ret = calc_pll_params(ref, freq, &pll_param);  in config_core_clk()
764 static int config_periph_clk(u32 ref, u32 freq)  in config_periph_clk()  argument
772 		ret = calc_pll_params(ref, freq, &pll_param);  in config_periph_clk()
842 static int config_ldb_clk(u32 ref, u32 freq)  in config_ldb_clk()  argument
849 	ret = calc_pll_params(ref, freq, &pll_param);  in config_ldb_clk()
859 static int config_ldb_clk(u32 ref, u32 freq)  in config_ldb_clk()  argument
886 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)  in mxc_set_clock()  argument
888 	freq *= SZ_DEC_1M;  in mxc_set_clock()
892 		if (config_core_clk(ref, freq))  in mxc_set_clock()
896 		if (config_periph_clk(ref, freq))  in mxc_set_clock()
900 		if (config_ddr_clk(freq))  in mxc_set_clock()
904 		if (config_nfc_clk(freq))  in mxc_set_clock()
908 		if (config_ldb_clk(ref, freq))  in mxc_set_clock()
948 	u32 freq;  in do_mx5_showclocks()  local
950 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
951 	printf("PLL1       %8d MHz\n", freq / 1000000);  in do_mx5_showclocks()
952 	freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
953 	printf("PLL2       %8d MHz\n", freq / 1000000);  in do_mx5_showclocks()
954 	freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
955 	printf("PLL3       %8d MHz\n", freq / 1000000);  in do_mx5_showclocks()
957 	freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
958 	printf("PLL4       %8d MHz\n", freq / 1000000);  in do_mx5_showclocks()