Lines Matching refs:SYSTEM_PLL1_800M_CLK

19 	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
24 	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
29 	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
33 	 {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
38 	 {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
43 	 {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
48 	 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
53 	 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
58 	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
63 	 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
68 	 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
73 	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
78 	 {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
83 	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
88 	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
93 	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
100 	  SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
103 	 {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
111 	 {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
117 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
121 	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
127 	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
131 	 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
136 	 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
141 	 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
146 	 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
152 	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
167 	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
172 	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
236 	 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
241 	 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
246 	 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
302 	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
307 	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
312 	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
381 	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
392 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
397 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
402 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
407 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
412 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
417 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
422 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
427 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
432 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
437 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
442 	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
457 	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
462 	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
467 	  VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,