355 	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |  in mxs_set_lcdclk()
365 	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |  in init_wdog_clk()
367 	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |  in init_wdog_clk()
369 	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |  in init_wdog_clk()
384 		clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |  in init_usb_clk()
387 		clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |  in init_usb_clk()
390 		clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |  in init_usb_clk()
405 		clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |  in init_uart_clk()
411 		clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |  in init_uart_clk()
417 		clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |  in init_uart_clk()
423 		clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |  in init_uart_clk()
442 		clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |  in init_clk_usdhc()
449 		clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |  in init_clk_usdhc()
467 	clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |  in set_clk_qspi()
502 	clock_set_target_val(ENET_AXI_CLK_ROOT, target);  in set_clk_enet()
507 	clock_set_target_val(ENET_REF_CLK_ROOT, target);  in set_clk_enet()
513 	clock_set_target_val(ENET_TIMER_CLK_ROOT, target);  in set_clk_enet()
554 	clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |  in dram_enable_bypass()
557 	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |  in dram_enable_bypass()
560 	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |  in dram_enable_bypass()
566 	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |  in dram_disable_bypass()
568 	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |  in dram_disable_bypass()
768 	clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |  in clock_init()
778 		clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |  in clock_init()
783 		clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |  in clock_init()
805 	clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |  in clock_init()