16 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;  variable
27 		pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);  in decode_frac_pll()
28 		pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);  in decode_frac_pll()
37 	pllout_div = readl(&ana_pll->frac_pllout_div_cfg);  in decode_frac_pll()
98 		pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);  in decode_sscg_pll()
99 		pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);  in decode_sscg_pll()
100 		pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);  in decode_sscg_pll()
113 		pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);  in decode_sscg_pll()
114 		pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);  in decode_sscg_pll()
115 		pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);  in decode_sscg_pll()
120 		pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);  in decode_sscg_pll()
121 		pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);  in decode_sscg_pll()
122 		pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);  in decode_sscg_pll()
127 		pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);  in decode_sscg_pll()
128 		pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);  in decode_sscg_pll()
129 		pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);  in decode_sscg_pll()
205 	pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);  in decode_sscg_pll()
577 	void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;  in dram_pll_init()
578 	void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;  in dram_pll_init()
659 		pll_cfg0 = &ana_pll->arm_pll_cfg0;  in frac_pll_init()
660 		pll_cfg1 = &ana_pll->arm_pll_cfg1;  in frac_pll_init()
701 		pll_cfg0 = &ana_pll->sys_pll1_cfg0;  in sscg_pll_init()
702 		pll_cfg1 = &ana_pll->sys_pll1_cfg1;  in sscg_pll_init()
703 		pll_cfg2 = &ana_pll->sys_pll1_cfg2;  in sscg_pll_init()
716 		pll_cfg0 = &ana_pll->sys_pll2_cfg0;  in sscg_pll_init()
717 		pll_cfg1 = &ana_pll->sys_pll2_cfg1;  in sscg_pll_init()
718 		pll_cfg2 = &ana_pll->sys_pll2_cfg2;  in sscg_pll_init()
731 		pll_cfg0 = &ana_pll->sys_pll3_cfg0;  in sscg_pll_init()
732 		pll_cfg1 = &ana_pll->sys_pll3_cfg1;  in sscg_pll_init()
733 		pll_cfg2 = &ana_pll->sys_pll3_cfg2;  in sscg_pll_init()
793 	setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |  in clock_init()
799 	setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |  in clock_init()