194 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
199 	sc_faddr_t start, end;  in get_owned_memreg()  local
205 		ret = sc_rm_get_memreg_info(-1, mr, &start, &end);  in get_owned_memreg()
210 		debug("0x%llx -- 0x%llx\n", start, end);  in get_owned_memreg()
211 		*addr_start = start;  in get_owned_memreg()
223 	sc_faddr_t start, end, end1;  in get_effective_memsize()  local
229 		err = get_owned_memreg(mr, &start, &end);  in get_effective_memsize()
231 			start = roundup(start, MEMSTART_ALIGNMENT);  in get_effective_memsize()
233 			if (start > end)  in get_effective_memsize()
237 			if (start >= PHYS_SDRAM_1 && start <= end1 &&  in get_effective_memsize()
238 			    (start <= CONFIG_SYS_TEXT_BASE &&  in get_effective_memsize()
255 	sc_faddr_t start, end, end1, end2;  in dram_init()  local
261 		err = get_owned_memreg(mr, &start, &end);  in dram_init()
263 			start = roundup(start, MEMSTART_ALIGNMENT);  in dram_init()
265 			if (start > end)  in dram_init()
268 			if (start >= PHYS_SDRAM_1 && start <= end1) {  in dram_init()
270 					gd->ram_size += end - start + 1;  in dram_init()
272 					gd->ram_size += end1 - start;  in dram_init()
273 			} else if (start >= PHYS_SDRAM_2 && start <= end2) {  in dram_init()
275 					gd->ram_size += end - start + 1;  in dram_init()
277 					gd->ram_size += end2 - start;  in dram_init()
292 	phys_addr_t start;  in dram_bank_sort()  local
296 		if (gd->bd->bi_dram[current_bank - 1].start >  in dram_bank_sort()
297 		    gd->bd->bi_dram[current_bank].start) {  in dram_bank_sort()
298 			start = gd->bd->bi_dram[current_bank - 1].start;  in dram_bank_sort()
301 			gd->bd->bi_dram[current_bank - 1].start =  in dram_bank_sort()
302 				gd->bd->bi_dram[current_bank].start;  in dram_bank_sort()
306 			gd->bd->bi_dram[current_bank].start = start;  in dram_bank_sort()
316 	sc_faddr_t start, end, end1, end2;  in dram_init_banksize()  local
324 		err = get_owned_memreg(mr, &start, &end);  in dram_init_banksize()
326 			start = roundup(start, MEMSTART_ALIGNMENT);  in dram_init_banksize()
327 			if (start > end) /* Small memory region, no use it */  in dram_init_banksize()
330 			if (start >= PHYS_SDRAM_1 && start <= end1) {  in dram_init_banksize()
331 				gd->bd->bi_dram[i].start = start;  in dram_init_banksize()
335 						end - start + 1;  in dram_init_banksize()
337 					gd->bd->bi_dram[i].size = end1 - start;  in dram_init_banksize()
341 			} else if (start >= PHYS_SDRAM_2 && start <= end2) {  in dram_init_banksize()
342 				gd->bd->bi_dram[i].start = start;  in dram_init_banksize()
346 						end - start + 1;  in dram_init_banksize()
348 					gd->bd->bi_dram[i].size = end2 - start;  in dram_init_banksize()
358 		gd->bd->bi_dram[0].start = PHYS_SDRAM_1;  in dram_init_banksize()
360 		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;  in dram_init_banksize()
408 	sc_faddr_t start, end;  in enable_caches()  local
420 		err = get_owned_memreg(mr, &start, &end);  in enable_caches()
422 			imx8_mem_map[i].virt = start;  in enable_caches()
423 			imx8_mem_map[i].phys = start;  in enable_caches()
424 			imx8_mem_map[i].size = get_block_size(start, end);  in enable_caches()
425 			imx8_mem_map[i].attrs = get_block_attrs(start);  in enable_caches()