1 // SPDX-License-Identifier: GPL-2.0+
3  * ddrmc DDR3 calibration code for NXP's VF610
12 #include <asm/arch/imx-regs.h>
15 #include "ddrmc-vf610-calibration.h"
36  * SW leveling supported operations - CR93[SW_LVL_MODE]:
38  * - 0x0 (b'00) - No leveling
40  * - 0x1 (b'01) - WRLVL_DL_X - It is not recommended to perform this tuning
41  *                             on HW designs utilizing non-flyback topology
47  *                             allowed, so the value in the filed doesn’t have
50  * - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
52  *                             centered in the window of valid read data.
54  * - 0x3 (b'11) - RDLVL_GTDL_0/1 - refers to the delay the PHY uses to un-gate
62 	int i, ret = -1;  in ddr_cal_get_first_edge_index()
66 	 * some wrong data)  in ddr_cal_get_first_edge_index()
70 		for (i = start; i <= max - samples; i++) {  in ddr_cal_get_first_edge_index()
72 				if (!test_bit(i - 1, bmap) &&  in ddr_cal_get_first_edge_index()
82 		for (i = start; i <= max - samples; i++) {  in ddr_cal_get_first_edge_index()
84 				if (test_bit(i - 1, bmap) &&  in ddr_cal_get_first_edge_index()
85 				    test_bit(i - 2, bmap) &&  in ddr_cal_get_first_edge_index()
86 				    test_bit(i - 3, bmap)) {  in ddr_cal_get_first_edge_index()
103 		if (i && (i % 32) == (32 - 1))  in bitmap_print()
110 	while (!(readl(&ddrmr->cr[94]) & DDRMC_CR94_SWLVL_OP_DONE))
113 	do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
117 	do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
121 	do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
125  * RDLVL_DL calibration:
128  * boot. Instead - one shall run this procedure on new boards
135 	int rdlvl_dl_0_min = -1, rdlvl_dl_0_max = -1;  in ddrmc_cal_dqs_to_dq()
136 	int rdlvl_dl_1_min = -1, rdlvl_dl_1_max = -1;  in ddrmc_cal_dqs_to_dq()
144 		(readl(&ddrmr->cr[105]) >> DDRMC_CR105_RDLVL_DL_0_OFF) & 0xFFFF;  in ddrmc_cal_dqs_to_dq()
145 	u16 rdlvl_dl_1_def = readl(&ddrmr->cr[110]) & 0xFFFF;  in ddrmc_cal_dqs_to_dq()
150 	debug("RDLVL: RDLVL_DL_0_DFL:\t 0x%x\n", rdlvl_dl_0_def);  in ddrmc_cal_dqs_to_dq()
151 	debug("RDLVL: RDLVL_DL_1_DFL:\t 0x%x\n", rdlvl_dl_1_def);  in ddrmc_cal_dqs_to_dq()
154 	 * Set/Read setup for calibration  in ddrmc_cal_dqs_to_dq()
156 	 * Values necessary for leveling from Vybrid RM [2] - page 1600  in ddrmc_cal_dqs_to_dq()
158 	writel(0x40703030, &ddrmr->cr[144]);  in ddrmc_cal_dqs_to_dq()
159 	writel(0x40, &ddrmr->cr[145]);  in ddrmc_cal_dqs_to_dq()
160 	writel(0x40, &ddrmr->cr[146]);  in ddrmc_cal_dqs_to_dq()
162 	tmp = readl(&ddrmr->cr[144]);  in ddrmc_cal_dqs_to_dq()
163 	debug("RDLVL: PHY_RDLVL_RES:\t 0x%x\n", (tmp >> 24) & 0xFF);// set 0x40  in ddrmc_cal_dqs_to_dq()
164 	debug("RDLVL: PHY_RDLV_LOAD:\t 0x%x\n", (tmp >> 16) & 0xFF);// set 0x70  in ddrmc_cal_dqs_to_dq()
165 	debug("RDLVL: PHY_RDLV_DLL:\t 0x%x\n", (tmp >> 8) & 0xFF); // set 0x30  in ddrmc_cal_dqs_to_dq()
166 	debug("RDLVL: PHY_RDLV_EN:\t 0x%x\n", tmp & 0xFF); //set 0x30  in ddrmc_cal_dqs_to_dq()
168 	tmp = readl(&ddrmr->cr[145]);  in ddrmc_cal_dqs_to_dq()
169 	debug("RDLVL: PHY_RDLV_RR:\t 0x%x\n", tmp & 0x3FF); //set 0x40  in ddrmc_cal_dqs_to_dq()
171 	tmp = readl(&ddrmr->cr[146]);  in ddrmc_cal_dqs_to_dq()
172 	debug("RDLVL: PHY_RDLV_RESP:\t 0x%x\n", tmp); //set 0x40  in ddrmc_cal_dqs_to_dq()
178 	 * If by any chance 1s are visible -> wrong number read  in ddrmc_cal_dqs_to_dq()
180 	clrbits_le32(&ddrmr->cr[101], DDRMC_CR101_PHY_RDLVL_EDGE);  in ddrmc_cal_dqs_to_dq()
182 	tmp = readl(&ddrmr->cr[101]);  in ddrmc_cal_dqs_to_dq()
183 	debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n",  in ddrmc_cal_dqs_to_dq()
186 	/* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */  in ddrmc_cal_dqs_to_dq()
187 	clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3),  in ddrmc_cal_dqs_to_dq()
189 	tmp = readl(&ddrmr->cr[93]);  in ddrmc_cal_dqs_to_dq()
190 	debug("RDLVL: SW_LVL_MODE:\t 0x%x\n",  in ddrmc_cal_dqs_to_dq()
193 	/* Start procedure - CR93[SWLVL_START] to ’b1 */  in ddrmc_cal_dqs_to_dq()
205 	debug("\nRDLVL: ---> RDLVL_DL_0\n");  in ddrmc_cal_dqs_to_dq()
209 		clrsetbits_le32(&ddrmr->cr[105],  in ddrmc_cal_dqs_to_dq()
220 		 * Read Responses - SWLVL_RESP_0  in ddrmc_cal_dqs_to_dq()
223 		 * -> 1 in the bit vector  in ddrmc_cal_dqs_to_dq()
225 		swlvl_rsp = (readl(&ddrmr->cr[94]) >>  in ddrmc_cal_dqs_to_dq()
234 	 * First test for rising edge 0x0 -> 0x1 in bitmap  in ddrmc_cal_dqs_to_dq()
241 	 * Secondly test for falling edge 0x1 -> 0x0 in bitmap  in ddrmc_cal_dqs_to_dq()
249 	rdlvl_dl_0 = (rdlvl_dl_0_max - rdlvl_dl_0_min) / 2;  in ddrmc_cal_dqs_to_dq()
251 	if (rdlvl_dl_0_max == -1 || rdlvl_dl_0_min == -1 || rdlvl_dl_0 <= 0) {  in ddrmc_cal_dqs_to_dq()
253 		debug("RDLVL: Using default - slice 0: %d!\n", rdlvl_dl_0_def);  in ddrmc_cal_dqs_to_dq()
257 	debug("\nRDLVL: ---> RDLVL_DL_1\n");  in ddrmc_cal_dqs_to_dq()
261 		clrsetbits_le32(&ddrmr->cr[110],  in ddrmc_cal_dqs_to_dq()
272 		 * Read Responses - SWLVL_RESP_1  in ddrmc_cal_dqs_to_dq()
275 		 * -> 1 in the bit vector  in ddrmc_cal_dqs_to_dq()
277 		swlvl_rsp = (readl(&ddrmr->cr[95]) >>  in ddrmc_cal_dqs_to_dq()
286 	 * First test for rising edge 0x0 -> 0x1 in bitmap  in ddrmc_cal_dqs_to_dq()
293 	 * Secondly test for falling edge 0x1 -> 0x0 in bitmap  in ddrmc_cal_dqs_to_dq()
301 	rdlvl_dl_1 = (rdlvl_dl_1_max - rdlvl_dl_1_min) / 2;  in ddrmc_cal_dqs_to_dq()
303 	if (rdlvl_dl_1_max == -1 || rdlvl_dl_1_min == -1 || rdlvl_dl_1 <= 0) {  in ddrmc_cal_dqs_to_dq()
305 		debug("RDLVL: Using default - slice 1: %d!\n", rdlvl_dl_1_def);  in ddrmc_cal_dqs_to_dq()
309 	debug("RDLVL: CALIBRATED: rdlvl_dl_0: 0x%x\t rdlvl_dl_1: 0x%x\n",  in ddrmc_cal_dqs_to_dq()
313 	writel(DDRMC_CR105_RDLVL_DL_0(rdlvl_dl_0), &ddrmr->cr[105]);  in ddrmc_cal_dqs_to_dq()
314 	writel(DDRMC_CR110_RDLVL_DL_1(rdlvl_dl_1), &ddrmr->cr[110]);  in ddrmc_cal_dqs_to_dq()
319 	/* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */  in ddrmc_cal_dqs_to_dq()
329  * WRLVL_DL calibration:
331  * For non-flyback memory architecture - where one have a single DDR3 x16
332  * memory - it is NOT necessary to perform "Write Leveling"