Lines Matching +full:0 +full:x12140000
10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
25 #define EXYNOS4_WATCHDOG_BASE 0x10060000
26 #define EXYNOS4_TZPC_BASE 0x10110000
27 #define EXYNOS4_DMC_CTRL_BASE 0x10400000
28 #define EXYNOS4_MIU_BASE 0x10600000
29 #define EXYNOS4_ACE_SFR_BASE 0x10830000
30 #define EXYNOS4_GPIO_PART2_BASE 0x11000000
31 #define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
32 #define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
33 #define EXYNOS4_GPIO_PART1_BASE 0x11400000
34 #define EXYNOS4_FIMD_BASE 0x11C00000
35 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
36 #define EXYNOS4_USBOTG_BASE 0x12480000
37 #define EXYNOS4_MMC_BASE 0x12510000
38 #define EXYNOS4_SROMC_BASE 0x12570000
39 #define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
40 #define EXYNOS4_USBPHY_BASE 0x125B0000
41 #define EXYNOS4_UART_BASE 0x13800000
42 #define EXYNOS4_I2C_BASE 0x13860000
43 #define EXYNOS4_ADC_BASE 0x13910000
44 #define EXYNOS4_SPI_BASE 0x13920000
45 #define EXYNOS4_PWMTIMER_BASE 0x139D0000
46 #define EXYNOS4_MODEM_BASE 0x13A00000
47 #define EXYNOS4_USBPHY_CONTROL 0x10020704
48 #define EXYNOS4_I2S_BASE 0xE2100000
60 #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
61 #define EXYNOS4X12_PRO_ID 0x10000000
62 #define EXYNOS4X12_SYSREG_BASE 0x10010000
63 #define EXYNOS4X12_POWER_BASE 0x10020000
64 #define EXYNOS4X12_SWRESET 0x10020400
65 #define EXYNOS4X12_USBPHY_CONTROL 0x10020704
66 #define EXYNOS4X12_CLOCK_BASE 0x10030000
67 #define EXYNOS4X12_SYSTIMER_BASE 0x10050000
68 #define EXYNOS4X12_WATCHDOG_BASE 0x10060000
69 #define EXYNOS4X12_TZPC_BASE 0x10110000
70 #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
71 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
72 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000
73 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
74 #define EXYNOS4X12_GPIO_PART2_0 0x11000000
75 #define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
76 #define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
77 #define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
78 #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
79 #define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
80 #define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
81 #define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
82 #define EXYNOS4X12_FIMD_BASE 0x11C00000
83 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
84 #define EXYNOS4X12_USBOTG_BASE 0x12480000
85 #define EXYNOS4X12_MMC_BASE 0x12510000
86 #define EXYNOS4X12_SROMC_BASE 0x12570000
87 #define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
88 #define EXYNOS4X12_USBPHY_BASE 0x125B0000
89 #define EXYNOS4X12_UART_BASE 0x13800000
90 #define EXYNOS4X12_I2C_BASE 0x13860000
91 #define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
106 #define EXYNOS5_I2C_SPACING 0x10000
108 #define EXYNOS5_AUDIOSS_BASE 0x03810000
109 #define EXYNOS5_GPIO_PART8_BASE 0x03860000
110 #define EXYNOS5_PRO_ID 0x10000000
111 #define EXYNOS5_CLOCK_BASE 0x10010000
112 #define EXYNOS5_POWER_BASE 0x10040000
113 #define EXYNOS5_SWRESET 0x10040400
114 #define EXYNOS5_SYSREG_BASE 0x10050000
115 #define EXYNOS5_TZPC_BASE 0x10100000
116 #define EXYNOS5_WATCHDOG_BASE 0x101D0000
117 #define EXYNOS5_ACE_SFR_BASE 0x10830000
118 #define EXYNOS5_DMC_PHY_BASE 0x10C00000
119 #define EXYNOS5_GPIO_PART5_BASE 0x10D10000
120 #define EXYNOS5_GPIO_PART6_BASE 0x10D10060
121 #define EXYNOS5_GPIO_PART7_BASE 0x10D100C0
122 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
123 #define EXYNOS5_GPIO_PART1_BASE 0x11400000
124 #define EXYNOS5_GPIO_PART2_BASE 0x114002E0
125 #define EXYNOS5_GPIO_PART3_BASE 0x11400C00
126 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
127 #define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
128 #define EXYNOS5_USB3PHY_BASE 0x12100000
129 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
130 #define EXYNOS5_USBPHY_BASE 0x12130000
131 #define EXYNOS5_USBOTG_BASE 0x12140000
132 #define EXYNOS5_MMC_BASE 0x12200000
133 #define EXYNOS5_SROMC_BASE 0x12250000
134 #define EXYNOS5_UART_BASE 0x12C00000
135 #define EXYNOS5_I2C_BASE 0x12C60000
136 #define EXYNOS5_SPI_BASE 0x12D20000
137 #define EXYNOS5_I2S_BASE 0x12D60000
138 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000
139 #define EXYNOS5_SPI_ISP_BASE 0x131A0000
140 #define EXYNOS5_GPIO_PART4_BASE 0x13400000
141 #define EXYNOS5_FIMD_BASE 0x14400000
142 #define EXYNOS5_DP_BASE 0x145B0000
149 #define EXYNOS5420_AUDIOSS_BASE 0x03810000
150 #define EXYNOS5420_GPIO_PART6_BASE 0x03860000
151 #define EXYNOS5420_PRO_ID 0x10000000
152 #define EXYNOS5420_CLOCK_BASE 0x10010000
153 #define EXYNOS5420_POWER_BASE 0x10040000
154 #define EXYNOS5420_SWRESET 0x10040400
155 #define EXYNOS5420_INFORM_BASE 0x10040800
156 #define EXYNOS5420_SPARE_BASE 0x10040900
157 #define EXYNOS5420_CPU_CONFIG_BASE 0x10042000
158 #define EXYNOS5420_CPU_STATUS_BASE 0x10042004
159 #define EXYNOS5420_SYSREG_BASE 0x10050000
160 #define EXYNOS5420_TZPC_BASE 0x100E0000
161 #define EXYNOS5420_WATCHDOG_BASE 0x101D0000
162 #define EXYNOS5420_ACE_SFR_BASE 0x10830000
163 #define EXYNOS5420_DMC_PHY_BASE 0x10C00000
164 #define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
165 #define EXYNOS5420_DMC_TZASC_BASE 0x10D40000
166 #define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
167 #define EXYNOS5420_MMC_BASE 0x12200000
168 #define EXYNOS5420_SROMC_BASE 0x12250000
169 #define EXYNOS5420_USB3PHY_BASE 0x12500000
170 #define EXYNOS5420_UART_BASE 0x12C00000
171 #define EXYNOS5420_I2C_BASE 0x12C60000
172 #define EXYNOS5420_I2C_8910_BASE 0x12E00000
173 #define EXYNOS5420_SPI_BASE 0x12D20000
174 #define EXYNOS5420_I2S_BASE 0x12D60000
175 #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
176 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000
177 #define EXYNOS5420_GPIO_PART2_BASE 0x13400000
178 #define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
179 #define EXYNOS5420_GPIO_PART4_BASE 0x13410000
180 #define EXYNOS5420_GPIO_PART5_BASE 0x14000000
181 #define EXYNOS5420_GPIO_PART1_BASE 0x14010000
182 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
183 #define EXYNOS5420_DP_BASE 0x145B0000
207 unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12; in s5p_set_cpu_id()
208 unsigned int cpu_rev = pro_id & 0x000000FF; in s5p_set_cpu_id()
211 case 0x200: in s5p_set_cpu_id()
213 s5p_cpu_id = 0x4210; in s5p_set_cpu_id()
214 s5p_cpu_rev = 0; in s5p_set_cpu_id()
216 case 0x210: in s5p_set_cpu_id()
218 s5p_cpu_id = 0x4210; in s5p_set_cpu_id()
221 case 0x412: in s5p_set_cpu_id()
223 s5p_cpu_id = 0x4412; in s5p_set_cpu_id()
226 case 0x520: in s5p_set_cpu_id()
228 s5p_cpu_id = 0x5250; in s5p_set_cpu_id()
230 case 0x420: in s5p_set_cpu_id()
232 s5p_cpu_id = 0x5420; in s5p_set_cpu_id()
234 case 0x422: in s5p_set_cpu_id()
237 * and has product id 0x5422 in s5p_set_cpu_id()
239 s5p_cpu_id = 0x5422; in s5p_set_cpu_id()
255 IS_SAMSUNG_TYPE(exynos4, 0x4)
256 IS_SAMSUNG_TYPE(exynos5, 0x5)
265 IS_EXYNOS_TYPE(exynos4210, 0x4210)
266 IS_EXYNOS_TYPE(exynos4412, 0x4412)
267 IS_EXYNOS_TYPE(exynos5250, 0x5250)
268 IS_EXYNOS_TYPE(exynos5420, 0x5420)
269 IS_EXYNOS_TYPE(exynos5422, 0x5422)
286 return 0; \