Lines Matching defs:exynos5_clock
515 struct exynos5_clock { struct
516 unsigned int apll_lock;
517 unsigned char res1[0xfc];
518 unsigned int apll_con0;
519 unsigned int apll_con1;
520 unsigned char res2[0xf8];
521 unsigned int src_cpu;
522 unsigned char res3[0x1fc];
523 unsigned int mux_stat_cpu;
524 unsigned char res4[0xfc];
525 unsigned int div_cpu0;
526 unsigned int div_cpu1;
527 unsigned char res5[0xf8];
528 unsigned int div_stat_cpu0;
529 unsigned int div_stat_cpu1;
530 unsigned char res6[0x1f8];
531 unsigned int gate_sclk_cpu;
532 unsigned char res7[0x1fc];
533 unsigned int clkout_cmu_cpu;
534 unsigned int clkout_cmu_cpu_div_stat;
535 unsigned char res8[0x5f8];
536 unsigned int armclk_stopctrl;
537 unsigned char res9[0x0c];
538 unsigned int parityfail_status;
539 unsigned int parityfail_clear;
540 unsigned char res10[0x8];
541 unsigned int pwr_ctrl;
542 unsigned int pwr_ctr2;
543 unsigned char res11[0xd8];
544 unsigned int apll_con0_l8;
545 unsigned int apll_con0_l7;
546 unsigned int apll_con0_l6;
547 unsigned int apll_con0_l5;
548 unsigned int apll_con0_l4;
549 unsigned int apll_con0_l3;
550 unsigned int apll_con0_l2;
551 unsigned int apll_con0_l1;
552 unsigned int iem_control;
553 unsigned char res12[0xdc];
554 unsigned int apll_con1_l8;
555 unsigned int apll_con1_l7;
556 unsigned int apll_con1_l6;
557 unsigned int apll_con1_l5;
558 unsigned int apll_con1_l4;
559 unsigned int apll_con1_l3;
560 unsigned int apll_con1_l2;
561 unsigned int apll_con1_l1;
562 unsigned char res13[0xe0];
563 unsigned int div_iem_l8;
564 unsigned int div_iem_l7;
565 unsigned int div_iem_l6;
566 unsigned int div_iem_l5;
567 unsigned int div_iem_l4;
568 unsigned int div_iem_l3;
569 unsigned int div_iem_l2;
570 unsigned int div_iem_l1;
571 unsigned char res14[0x2ce0];
572 unsigned int mpll_lock;
573 unsigned char res15[0xfc];
574 unsigned int mpll_con0;
575 unsigned int mpll_con1;
576 unsigned char res16[0xf8];
577 unsigned int src_core0;
578 unsigned int src_core1;
579 unsigned char res17[0xf8];
580 unsigned int src_mask_core;
581 unsigned char res18[0x100];
582 unsigned int mux_stat_core1;
583 unsigned char res19[0xf8];
584 unsigned int div_core0;
585 unsigned int div_core1;
586 unsigned int div_sysrgt;
587 unsigned char res20[0xf4];
588 unsigned int div_stat_core0;
589 unsigned int div_stat_core1;
590 unsigned int div_stat_sysrgt;
591 unsigned char res21[0x2f4];
592 unsigned int gate_ip_core;
593 unsigned int gate_ip_sysrgt;
594 unsigned char res22[0x8];
595 unsigned int c2c_monitor;
596 unsigned char res23[0xec];
597 unsigned int clkout_cmu_core;
598 unsigned int clkout_cmu_core_div_stat;
599 unsigned char res24[0x5f8];
600 unsigned int dcgidx_map0;
601 unsigned int dcgidx_map1;
602 unsigned int dcgidx_map2;
603 unsigned char res25[0x14];
604 unsigned int dcgperf_map0;
605 unsigned int dcgperf_map1;
606 unsigned char res26[0x18];
607 unsigned int dvcidx_map;
608 unsigned char res27[0x1c];
609 unsigned int freq_cpu;
610 unsigned int freq_dpm;
611 unsigned char res28[0x18];
612 unsigned int dvsemclk_en;
613 unsigned int maxperf;
614 unsigned char res29[0xf78];
615 unsigned int c2c_config;
616 unsigned char res30[0x24fc];
617 unsigned int div_acp;
618 unsigned char res31[0xfc];
619 unsigned int div_stat_acp;
620 unsigned char res32[0x1fc];
621 unsigned int gate_ip_acp;
622 unsigned char res33[0xfc];
623 unsigned int div_syslft;
624 unsigned char res34[0xc];
625 unsigned int div_stat_syslft;
626 unsigned char res35[0x1c];
627 unsigned int gate_ip_syslft;
628 unsigned char res36[0xcc];
629 unsigned int clkout_cmu_acp;
630 unsigned int clkout_cmu_acp_div_stat;
631 unsigned char res37[0x8];
632 unsigned int ufmc_config;
633 unsigned char res38[0x38ec];
634 unsigned int div_isp0;
635 unsigned int div_isp1;
636 unsigned int div_isp2;
637 unsigned char res39[0xf4];
638 unsigned int div_stat_isp0;
639 unsigned int div_stat_isp1;
640 unsigned int div_stat_isp2;
641 unsigned char res40[0x3f4];
642 unsigned int gate_ip_isp0;
643 unsigned int gate_ip_isp1;
644 unsigned char res41[0xf8];
645 unsigned int gate_sclk_isp;
646 unsigned char res42[0xc];
647 unsigned int mcuisp_pwr_ctrl;
648 unsigned char res43[0xec];
649 unsigned int clkout_cmu_isp;
650 unsigned int clkout_cmu_isp_div_stat;
651 unsigned char res44[0x3618];
652 unsigned int cpll_lock;
653 unsigned char res45[0xc];
654 unsigned int epll_lock;
655 unsigned char res46[0xc];
656 unsigned int vpll_lock;
657 unsigned char res47[0xc];
658 unsigned int gpll_lock;
659 unsigned char res48[0xcc];
660 unsigned int cpll_con0;
661 unsigned int cpll_con1;
662 unsigned char res49[0x8];
663 unsigned int epll_con0;
664 unsigned int epll_con1;
665 unsigned int epll_con2;
666 unsigned char res50[0x4];
667 unsigned int vpll_con0;
668 unsigned int vpll_con1;
669 unsigned int vpll_con2;
670 unsigned char res51[0x4];
671 unsigned int gpll_con0;
672 unsigned int gpll_con1;
673 unsigned char res52[0xb8];
674 unsigned int src_top0;
675 unsigned int src_top1;
676 unsigned int src_top2;
677 unsigned int src_top3;
678 unsigned int src_gscl;
679 unsigned char res53[0x8];
680 unsigned int src_disp1_0;
681 unsigned char res54[0x10];
682 unsigned int src_mau;
683 unsigned int src_fsys;
684 unsigned int src_gen;
685 unsigned char res55[0x4];
686 unsigned int src_peric0;
687 unsigned int src_peric1;
688 unsigned char res56[0x18];
689 unsigned int sclk_src_isp;
690 unsigned char res57[0x9c];
691 unsigned int src_mask_top;
692 unsigned char res58[0xc];
693 unsigned int src_mask_gscl;
694 unsigned char res59[0x8];
695 unsigned int src_mask_disp1_0;
696 unsigned char res60[0x4];
697 unsigned int src_mask_mau;
698 unsigned char res61[0x8];
699 unsigned int src_mask_fsys;
700 unsigned int src_mask_gen;
701 unsigned char res62[0x8];
702 unsigned int src_mask_peric0;
703 unsigned int src_mask_peric1;
704 unsigned char res63[0x18];
705 unsigned int src_mask_isp;
706 unsigned char res67[0x9c];
707 unsigned int mux_stat_top0;
708 unsigned int mux_stat_top1;
709 unsigned int mux_stat_top2;
710 unsigned int mux_stat_top3;
711 unsigned char res68[0xf0];
712 unsigned int div_top0;
713 unsigned int div_top1;
714 unsigned char res69[0x8];
715 unsigned int div_gscl;
716 unsigned char res70[0x8];
717 unsigned int div_disp1_0;
718 unsigned char res71[0xc];
719 unsigned int div_gen;
720 unsigned char res72[0x4];
721 unsigned int div_mau;
722 unsigned int div_fsys0;
723 unsigned int div_fsys1;
724 unsigned int div_fsys2;
725 unsigned char res73[0x4];
726 unsigned int div_peric0;
727 unsigned int div_peric1;
728 unsigned int div_peric2;
729 unsigned int div_peric3;
730 unsigned int div_peric4;
731 unsigned int div_peric5;
732 unsigned char res74[0x10];
733 unsigned int sclk_div_isp;
734 unsigned char res75[0xc];
735 unsigned int div2_ratio0;
736 unsigned int div2_ratio1;
737 unsigned char res76[0x8];
738 unsigned int div4_ratio;
739 unsigned char res77[0x6c];
740 unsigned int div_stat_top0;
741 unsigned int div_stat_top1;
742 unsigned char res78[0x8];
743 unsigned int div_stat_gscl;
744 unsigned char res79[0x8];
745 unsigned int div_stat_disp1_0;
746 unsigned char res80[0xc];
747 unsigned int div_stat_gen;
748 unsigned char res81[0x4];
749 unsigned int div_stat_mau;
750 unsigned int div_stat_fsys0;
751 unsigned int div_stat_fsys1;
752 unsigned int div_stat_fsys2;
753 unsigned char res82[0x4];
754 unsigned int div_stat_peric0;
755 unsigned int div_stat_peric1;
756 unsigned int div_stat_peric2;
757 unsigned int div_stat_peric3;
758 unsigned int div_stat_peric4;
759 unsigned int div_stat_peric5;
760 unsigned char res83[0x10];
761 unsigned int sclk_div_stat_isp;
762 unsigned char res84[0xc];
763 unsigned int div2_stat0;
764 unsigned int div2_stat1;
765 unsigned char res85[0x8];
766 unsigned int div4_stat;
767 unsigned char res86[0x184];
768 unsigned int gate_top_sclk_disp1;
769 unsigned int gate_top_sclk_gen;
770 unsigned char res87[0xc];
771 unsigned int gate_top_sclk_mau;
772 unsigned int gate_top_sclk_fsys;
773 unsigned char res88[0xc];
774 unsigned int gate_top_sclk_peric;
775 unsigned char res89[0x1c];
776 unsigned int gate_top_sclk_isp;
777 unsigned char res90[0xac];
778 unsigned int gate_ip_gscl;
779 unsigned char res91[0x4];
780 unsigned int gate_ip_disp1;
781 unsigned int gate_ip_mfc;
782 unsigned int gate_ip_g3d;
783 unsigned int gate_ip_gen;
784 unsigned char res92[0xc];
785 unsigned int gate_ip_fsys;
786 unsigned char res93[0x8];
787 unsigned int gate_ip_peric;
788 unsigned char res94[0xc];
789 unsigned int gate_ip_peris;
790 unsigned char res95[0x1c];
791 unsigned int gate_block;
792 unsigned char res96[0x1c];
793 unsigned int mcuiop_pwr_ctrl;
794 unsigned char res97[0x5c];
795 unsigned int clkout_cmu_top;
796 unsigned int clkout_cmu_top_div_stat;
797 unsigned char res98[0x37f8];
798 unsigned int src_lex;
799 unsigned char res99[0x1fc];
800 unsigned int mux_stat_lex;
801 unsigned char res100[0xfc];
802 unsigned int div_lex;
803 unsigned char res101[0xfc];
804 unsigned int div_stat_lex;
805 unsigned char res102[0x1fc];
806 unsigned int gate_ip_lex;
807 unsigned char res103[0x1fc];
808 unsigned int clkout_cmu_lex;
809 unsigned int clkout_cmu_lex_div_stat;
810 unsigned char res104[0x3af8];
811 unsigned int div_r0x;
812 unsigned char res105[0xfc];
813 unsigned int div_stat_r0x;
814 unsigned char res106[0x1fc];
815 unsigned int gate_ip_r0x;
816 unsigned char res107[0x1fc];
817 unsigned int clkout_cmu_r0x;
818 unsigned int clkout_cmu_r0x_div_stat;
819 unsigned char res108[0x3af8];
820 unsigned int div_r1x;
821 unsigned char res109[0xfc];
822 unsigned int div_stat_r1x;
823 unsigned char res110[0x1fc];
824 unsigned int gate_ip_r1x;
825 unsigned char res111[0x1fc];
826 unsigned int clkout_cmu_r1x;
827 unsigned int clkout_cmu_r1x_div_stat;
828 unsigned char res112[0x3608];
829 unsigned int bpll_lock;
830 unsigned char res113[0xfc];
831 unsigned int bpll_con0;
832 unsigned int bpll_con1;
833 unsigned char res114[0xe8];
834 unsigned int src_cdrex;
835 unsigned char res115[0x1fc];
836 unsigned int mux_stat_cdrex;
837 unsigned char res116[0xfc];
838 unsigned int div_cdrex;
839 unsigned char res117[0xfc];
840 unsigned int div_stat_cdrex;
841 unsigned char res118[0x2fc];
842 unsigned int gate_ip_cdrex;
843 unsigned char res119[0x10];
844 unsigned int dmc_freq_ctrl;
845 unsigned char res120[0x4];
846 unsigned int drex2_pause;
847 unsigned char res121[0xe0];
848 unsigned int clkout_cmu_cdrex;
849 unsigned int clkout_cmu_cdrex_div_stat;
850 unsigned char res122[0x8];
851 unsigned int lpddr3phy_ctrl;
852 unsigned int lpddr3phy_con0;
853 unsigned int lpddr3phy_con1;
854 unsigned int lpddr3phy_con2;
855 unsigned int lpddr3phy_con3;
856 unsigned int pll_div2_sel;
857 unsigned char res123[0xf5d8];