Lines Matching +full:0 +full:x00010004
14 #define NOT_AVAILABLE 0
15 #define DATA_MASK 0xFFFFF
17 #define ENABLE_BIT 0x1
18 #define DISABLE_BIT 0x0
19 #define CA_SWAP_EN (1 << 0)
25 #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
26 #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
27 #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
28 #define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
29 #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
39 #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
45 #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
47 #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
58 #define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
61 #define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
64 DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
70 * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
71 * we need to set half 0x10 to the membaseconfigx registers
74 #define DMC_CHIP_BASE_0 0x10
75 #define DMC_CHIP_BASE_1 0x50
76 #define DMC_CHIP_MASK 0x7C0
78 #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
79 #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
81 #define DMC_PRECHCONFIG_VAL 0xFF000000
82 #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
84 #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
95 #define CLK_STOP_EN (1 << 0)
100 #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
102 #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
104 #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
106 #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
107 #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
108 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
110 #define DMC_CONCONTROL_VAL 0x1FFF2101
119 #define HPM_RATIO 0x2
120 #define COPY_RATIO 0x0
122 /* CLK_DIV_CPU1 = 0x00000003 */
127 #define CLK_SRC_CORE0_VAL 0x00000000
130 #define CLK_SRC_CORE1_VAL 0x100
133 #define CLK_DIV_CORE0_VAL 0x00120000
136 #define CLK_DIV_CORE1_VAL 0x07070700
139 #define CLK_DIV_SYSRGT_VAL 0x00000111
142 #define CLK_DIV_ACP_VAL 0x12
145 #define CLK_DIV_SYSLFT_VAL 0x00000311
147 #define MUX_APLL_SEL_MASK (1 << 0)
154 #define MUX_BPLL_SEL_MASK (1 << 0)
165 #define CLK_REG_DISABLE 0x0
166 #define TOP2_VAL 0x0110000
172 | (SPI0_ISP_SEL << 0)
174 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
175 #define SPI0_ISP_RATIO 0xf
176 #define SPI1_ISP_RATIO 0xf
178 | (SPI0_ISP_RATIO << 0)
181 #define MMC2_RATIO_MASK 0xf
182 #define MMC2_RATIO_VAL 0x3
183 #define MMC2_RATIO_OFFSET 0
185 #define MMC2_PRE_RATIO_MASK 0xff
186 #define MMC2_PRE_RATIO_VAL 0x9
189 #define MMC3_RATIO_MASK 0xf
190 #define MMC3_RATIO_VAL 0x1
193 #define MMC3_PRE_RATIO_MASK 0xff
194 #define MMC3_PRE_RATIO_VAL 0x0
198 #define CLK_SRC_LEX_VAL 0x0
201 #define CLK_DIV_LEX_VAL 0x10
204 #define CLK_DIV_R0X_VAL 0x10
207 #define CLK_DIV_R1X_VAL 0x10
210 #define CLK_DIV_ISP2_VAL 0x1
216 #define CLK_SRC_KFC_VAL 0x00008001
219 #define CLK_DIV_KFC_VAL 0x03300110
222 #define CLK_DIV2_RATIO 0x10111150
225 #define CLK_DIV4_RATIO 0x00000003
228 #define CLK_DIV_G2D 0x00000010
234 #define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
240 #define AUDIO0_SEL_EPLL (0x6 << 28)
241 #define AUDIO0_RATIO 0x5
242 #define PCM0_RATIO 0x3
247 #define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
248 #define BPLL_SEL_MASK 0x7
251 #define DDR3PHY_CTRL_PHY_RESET (1 << 0)
252 #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
254 #define PHY_CON0_RESET_VAL 0x17020a40
259 #define PHY_CON1_RESET_VAL 0x09210100
260 #define RDLVL_PASS_ADJ_VAL 0x6
262 #define CTRL_GATEDURADJ_MASK (0xf << 20)
263 #define READ_LEVELLING_DDR3 0x0100
265 #define PHY_CON2_RESET_VAL 0x00010004
270 #define RDLVL_INCR_ADJ (0x1 << 16)
273 #define DREX_PAUSE_EN (1 << 0)
278 #define PHY_CON0_VAL 0x17021A00
280 #define PHY_CON12_RESET_VAL 0x10100070
281 #define PHY_CON12_VAL 0x10107F50
285 #define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET)
288 #define CTRL_FORCE_MASK (0x7F << 8)
289 #define CTRL_FINE_LOCKED 0x7
291 #define CTRL_OFFSETD_RESET_VAL 0x8
292 #define CTRL_OFFSETD_VAL 0x7F
294 #define CTRL_OFFSETR0 0x7F
295 #define CTRL_OFFSETR1 0x7F
296 #define CTRL_OFFSETR2 0x7F
297 #define CTRL_OFFSETR3 0x7F
298 #define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
302 #define PHY_CON4_RESET_VAL 0x08080808
304 #define CTRL_OFFSETW0 0x7F
305 #define CTRL_OFFSETW1 0x7F
306 #define CTRL_OFFSETW2 0x7F
307 #define CTRL_OFFSETW3 0x7F
308 #define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
312 #define PHY_CON6_RESET_VAL 0x08080808
314 #define PHY_CON14_RESET_VAL 0x001F0000
315 #define CTRL_PULLD_DQS 0xF
316 #define CTRL_PULLD_DQS_OFFSET 0
319 #define PHY_CON16_RESET_VAL 0x08000304
324 #define ZQ_DONE (1 << 0)
328 #define CTRL_RDLVL_GATE_DISABLE 0
332 #define DIRECT_CMD_NOP 0x07000000
333 #define DIRECT_CMD_PALL 0x01000000
334 #define DIRECT_CMD_ZQINIT 0x0a000000
339 #define DIRECT_CMD_MRS1 0x71C00
340 #define DIRECT_CMD_MRS2 0x10BFC
341 #define DIRECT_CMD_MRS3 0x0050C
342 #define DIRECT_CMD_MRS4 0x00868
343 #define DIRECT_CMD_MRS5 0x00C04
350 #define PHY_CON39_VAL_48_OHM 0x09240924
351 #define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
352 #define PHY_CON39_VAL_34_OHM 0x0DB60DB6
353 #define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
356 #define CTRL_RDLAT_OFFSET 0
358 #define CMD_DEFAULT_LPDDR3 0xF
359 #define CMD_DEFUALT_OFFSET 0
360 #define T_WRDATA_EN 0x7
361 #define T_WRDATA_EN_DDR3 0x8
363 #define T_WRDATA_EN_MASK 0x1f
365 #define PHY_CON31_VAL 0x0C183060
366 #define PHY_CON32_VAL 0x60C18306
367 #define PHY_CON33_VAL 0x00000030
369 #define PHY_CON31_RESET_VAL 0x0
370 #define PHY_CON32_RESET_VAL 0x0
371 #define PHY_CON33_RESET_VAL 0x0
381 #define DMC_MEMCONTROL_VAL 0x00312700
382 #define CLK_STOP_EN (1 << 0)
386 #define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
387 #define MEMBASECONFIG_CHIP_MASK_OFFSET 0
388 #define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
389 #define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
392 #define MEMCONFIG_VAL 0x1323
393 #define PRECHCONFIG_DEFAULT_VAL 0xFF000000
394 #define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
396 #define TIMINGAREF_VAL 0x5d
397 #define TIMINGROW_VAL 0x345A8692
398 #define TIMINGDATA_VAL 0x3630065C
399 #define TIMINGPOWER_VAL 0x50380336
402 #define BRBRSVCONTROL_VAL 0x00000033
403 #define BRBRSVCONFIG_VAL 0x88778877
409 #define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
414 #define PHY_CONTROL0_RESET_VAL 0x0
421 #define IMP_OUTPUT_DRV_40_OHM 0x5
422 #define IMP_OUTPUT_DRV_30_OHM 0x7
430 #define CA_ADR_DRVR_DS_OFFSET 0
433 #define PHY_CON42_CTRL_RDLAT_SHIFT 0
443 #define APLL_CON1_VAL (0x00203800)
446 #define MPLL_CON1_VAL (0x00203800)
449 #define CPLL_CON1_VAL (0x00203800)
455 #define GPLL_CON1_VAL (0x00203800)
458 #define EPLL_CON1_VAL 0x00000000
459 #define EPLL_CON2_VAL 0x00000080
462 #define VPLL_CON1_VAL 0x00000000
463 #define VPLL_CON2_VAL 0x00000080
470 #define BPLL_CON1_VAL 0x00203800
483 #define CLK_DIV_ISP0_VAL 0x31
484 #define CLK_DIV_ISP1_VAL 0x0
487 #define CLK_SRC_FSYS0_VAL 0x66666
488 #define CLK_DIV_FSYS0_VAL 0x0BB00000
493 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
494 #define MUX_HPM_SEL 0
495 #define MUX_CPU_SEL 0
503 #define CLK_SRC_CDREX_VAL 0x1
512 #define MCLK_CDREX2_RATIO 0x0
513 #define ACLK_EFCON_RATIO 0x1
514 #define MCLK_DPHY_RATIO 0x1
515 #define MCLK_CDREX_RATIO 0x1
516 #define ACLK_C2C_200_RATIO 0x1
517 #define C2C_CLK_400_RATIO 0x1
518 #define PCLK_CDREX_RATIO 0x1
519 #define ACLK_CDREX_RATIO 0x1
527 #define MUX_ACLK_300_GSCL_SEL 0x0
528 #define MUX_ACLK_300_GSCL_MID_SEL 0x0
529 #define MUX_ACLK_400_G3D_MID_SEL 0x0
530 #define MUX_ACLK_333_SEL 0x0
531 #define MUX_ACLK_300_DISP1_SEL 0x0
532 #define MUX_ACLK_300_DISP1_MID_SEL 0x0
533 #define MUX_ACLK_200_SEL 0x0
534 #define MUX_ACLK_166_SEL 0x0
545 #define MUX_ACLK_400_G3D_SEL 0x1
546 #define MUX_ACLK_400_ISP_SEL 0x0
547 #define MUX_ACLK_400_IOP_SEL 0x0
548 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
549 #define MUX_ACLK_300_GSCL_MID1_SEL 0x0
550 #define MUX_ACLK_300_DISP1_MID1_SEL 0x0
559 #define MUX_GPLL_SEL 0x1
560 #define MUX_BPLL_USER_SEL 0x0
561 #define MUX_MPLL_USER_SEL 0x0
562 #define MUX_VPLL_SEL 0x1
563 #define MUX_EPLL_SEL 0x1
564 #define MUX_CPLL_SEL 0x1
565 #define VPLLSRC_SEL 0x0
574 #define MUX_ACLK_333_SUB_SEL 0x1
575 #define MUX_ACLK_400_SUB_SEL 0x1
576 #define MUX_ACLK_266_ISP_SUB_SEL 0x1
577 #define MUX_ACLK_266_GPS_SUB_SEL 0x0
578 #define MUX_ACLK_300_GSCL_SUB_SEL 0x1
579 #define MUX_ACLK_266_GSCL_SUB_SEL 0x1
580 #define MUX_ACLK_300_DISP1_SUB_SEL 0x1
581 #define MUX_ACLK_200_DISP1_SUB_SEL 0x1
597 #define ACLK_300_DISP1_RATIO 0x2
598 #define ACLK_400_G3D_RATIO 0x0
599 #define ACLK_333_RATIO 0x0
600 #define ACLK_266_RATIO 0x2
601 #define ACLK_200_RATIO 0x3
602 #define ACLK_166_RATIO 0x1
603 #define ACLK_133_RATIO 0x1
604 #define ACLK_66_RATIO 0x5
616 #define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
617 #define ACLK_66_PRE_RATIO 0x1
618 #define ACLK_400_ISP_RATIO 0x1
619 #define ACLK_400_IOP_RATIO 0x1
620 #define ACLK_300_GSCL_RATIO 0x2
669 #define SPI1_RATIO 0x7
670 #define SPI0_RATIO 0xf
671 #define SPI1_SUB_RATIO 0x0
672 #define SPI0_SUB_RATIO 0x0
676 | (SPI0_RATIO << 0)))
679 #define SPI2_RATIO 0xf
680 #define SPI2_SUB_RATIO 0x0
682 | (SPI2_RATIO << 0))
686 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
693 #define CLK_SRC_DISP1_0_VAL 0x6
696 #define APLL_FOUT (1 << 0)
703 #define CPU_CONFIG_STATUS_OFFSET 0x80
704 #define CPU_RST_FLAG_VAL 0xFCBA0D10
705 #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
708 #define APLL_CON1_VAL (0x0020F300)
711 #define MPLL_CON1_VAL (0x0020F300)
715 #define CPLL_CON1_VAL 0x0020f300
718 #define DPLL_CON1_VAL (0x0020F300)
725 #define EPLL_CON1_VAL 0x00000000
726 #define EPLL_CON2_VAL 0x00000080
729 #define VPLL_CON1_VAL 0x0020f300
733 #define RPLL_CON1_VAL 0x00000000
734 #define RPLL_CON2_VAL 0x00000080
737 #define BPLL_CON1_VAL 0x0020f300
740 #define SPLL_CON1_VAL 0x0020f300
743 #define IPLL_CON1_VAL 0x00000080
746 #define KPLL_CON1_VAL 0x200000
749 #define CLK_SRC_ISP_VAL 0x33366000
750 #define CLK_DIV_ISP0_VAL 0x13131300
751 #define CLK_DIV_ISP1_VAL 0xbb110202
755 #define CLK_SRC_FSYS0_VAL 0x33033300
756 #define CLK_DIV_FSYS0_VAL 0x0
757 #define CLK_DIV_FSYS1_VAL 0x04f13c4f
758 #define CLK_DIV_FSYS2_VAL 0x041d0000
761 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
763 #define MUX_CPU_SEL 0
771 #define CLK_SRC_CDREX_VAL 0x00000011
774 #define CLK_DIV_CDREX0_VAL 0x30010100
775 #define CLK_DIV_CDREX1_VAL 0x300
777 #define CLK_DIV_CDREX_VAL 0x17010100
780 #define CLK_DIV_CPU0_VAL 0x01440020
783 #define CLK_SRC_TOP0_VAL 0x12221222
784 #define CLK_SRC_TOP1_VAL 0x00100200
785 #define CLK_SRC_TOP2_VAL 0x11101000
786 #define CLK_SRC_TOP3_VAL 0x11111111
787 #define CLK_SRC_TOP4_VAL 0x11110111
788 #define CLK_SRC_TOP5_VAL 0x11111101
789 #define CLK_SRC_TOP6_VAL 0x11110111
790 #define CLK_SRC_TOP7_VAL 0x00022200
793 #define CLK_DIV_TOP0_VAL 0x23712311
794 #define CLK_DIV_TOP1_VAL 0x13100B00
795 #define CLK_DIV_TOP2_VAL 0x11101100
848 #define SPI2_RATIO 0x1
849 #define SPI1_RATIO 0x1
850 #define SPI0_RATIO 0x1
856 #define PCM2_RATIO 0x3
857 #define PCM1_RATIO 0x3
862 #define AUDIO2_RATIO 0x5
863 #define AUDIO1_RATIO 0x5
864 #define AUDIO0_RATIO 0x5
870 #define SPI2_PRE_RATIO 0x2
871 #define SPI1_PRE_RATIO 0x2
872 #define SPI0_PRE_RATIO 0x2
878 #define CLK_SRC_DISP1_0_VAL 0x10666600
879 #define CLK_DIV_DISP1_0_VAL 0x01050211
881 #define APLL_FOUT (1 << 0)
882 #define KPLL_FOUT (1 << 0)
884 #define CLK_DIV_CPERI1_VAL 0x3f3f0000
901 * @return 0 if ok, SETUP_ERR_... if there is a problem
916 * @return 0 if ok, -1 on error