31 struct mem_timings mem = {  variable
54 		writel((mem.control1 | (1 << mem.dll_resync)),  in phy_control_reset()
56 		writel((mem.control1 | (0 << mem.dll_resync)),  in phy_control_reset()
59 		writel((mem.control0 | (0 << mem.dll_on)),  in phy_control_reset()
61 		writel((mem.control0 | (1 << mem.dll_on)),  in phy_control_reset()
75 		writel(mem.direct_cmd_msr[i] | mask,  in dmc_config_mrs()
87 	writel(mem.control1, &dmc->phycontrol1);  in dmc_init()
94 	writel(mem.zqcontrol, &dmc->phyzqcontrol);  in dmc_init()
105 	writel(mem.control1, &dmc->phycontrol1);  in dmc_init()
108 	writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);  in dmc_init()
110 	writel(mem.control2, &dmc->phycontrol2);  in dmc_init()
113 	writel(mem.concontrol, &dmc->concontrol);  in dmc_init()
122 	writel(mem.memcontrol, &dmc->memcontrol);  in dmc_init()
124 	writel(mem.memconfig0, &dmc->memconfig0);  in dmc_init()
125 	writel(mem.memconfig1, &dmc->memconfig1);  in dmc_init()
128 	writel(mem.prechconfig, &dmc->prechconfig);  in dmc_init()
133 	writel(mem.timingref, &dmc->timingref);  in dmc_init()
134 	writel(mem.timingrow, &dmc->timingrow);  in dmc_init()
135 	writel(mem.timingdata, &dmc->timingdata);  in dmc_init()
136 	writel(mem.timingpower, &dmc->timingpower);  in dmc_init()
165 	writel((mem.concontrol | AREF_EN), &dmc->concontrol);  in dmc_init()