Lines Matching +full:0 +full:xf
32 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
33 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
34 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
35 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
36 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
37 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
38 {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
39 {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
40 {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
41 {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
42 {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
43 {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
44 {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
45 {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
46 {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
47 {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
48 {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
49 {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
50 {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24},
51 {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
52 {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
53 {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4},
54 {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16},
55 {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8},
56 {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
57 {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
58 {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
59 {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
60 {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
67 {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
68 {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
69 {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
70 {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
71 {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
72 {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
73 {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
74 {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
75 {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
76 {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
77 {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
78 {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
79 {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8},
80 {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16},
81 {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24},
82 {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
83 {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
84 {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
85 {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
86 {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
87 {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
88 {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
89 {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0},
90 {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8},
91 {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
92 {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
93 {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
94 {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
95 {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
96 {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
103 { 192000000, 0, 48, 3, 1, 0 },
104 { 180000000, 0, 45, 3, 1, 0 },
107 { 49152000, 0, 49, 3, 3, 9961 },
108 { 45158400, 0, 45, 3, 3, 10381 },
109 { 180633600, 0, 45, 3, 1, 10381 }
115 unsigned long m, p, s = 0, mask, fout; in exynos_get_pll_clk()
127 mask = 0x3ff; in exynos_get_pll_clk()
129 mask = 0x1ff; in exynos_get_pll_clk()
134 p = (r >> 8) & 0x3f; in exynos_get_pll_clk()
135 /* SDIV [2:0] */ in exynos_get_pll_clk()
136 s = r & 0x7; in exynos_get_pll_clk()
141 k = k & 0xffff; in exynos_get_pll_clk()
145 k = k & 0xfff; in exynos_get_pll_clk()
165 return 0; in exynos_get_pll_clk()
189 unsigned long r, k = 0; in exynos4_get_pll_clk()
208 return 0; in exynos4_get_pll_clk()
219 unsigned long r, k = 0; in exynos4x12_get_pll_clk()
238 return 0; in exynos4x12_get_pll_clk()
249 unsigned long r, k = 0, fout; in exynos5_get_pll_clk()
272 return 0; in exynos5_get_pll_clk()
296 if (fout_sel == 0) in exynos5_get_pll_clk()
308 unsigned long r, k = 0; in exynos542x_get_pll_clk()
337 return 0; in exynos542x_get_pll_clk()
353 for (i = 0; info[i].id != PERIPH_ID_NONE; i++) { in get_clk_bit_info()
367 unsigned long sclk = 0; in exynos5_get_periph_rate()
368 unsigned int src = 0, div = 0, sub_div = 0; in exynos5_get_periph_rate()
432 if (bit_info->src_bit >= 0) in exynos5_get_periph_rate()
447 return 0; in exynos5_get_periph_rate()
451 if (bit_info->div_bit >= 0) in exynos5_get_periph_rate()
455 if (bit_info->prediv_bit >= 0) in exynos5_get_periph_rate()
466 unsigned long sclk = 0; in exynos542x_get_periph_rate()
467 unsigned int src = 0, div = 0, sub_div = 0; in exynos542x_get_periph_rate()
523 if (bit_info->src_bit >= 0) in exynos542x_get_periph_rate()
541 return 0; in exynos542x_get_periph_rate()
545 if (bit_info->div_bit >= 0) in exynos542x_get_periph_rate()
549 if (bit_info->prediv_bit >= 0) in exynos542x_get_periph_rate()
564 return 0; in clock_get_periph_rate()
580 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ in exynos4_get_arm_clk()
581 core_ratio = (div >> 0) & 0x7; in exynos4_get_arm_clk()
582 core2_ratio = (div >> 28) & 0x7; in exynos4_get_arm_clk()
602 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ in exynos4x12_get_arm_clk()
603 core_ratio = (div >> 0) & 0x7; in exynos4x12_get_arm_clk()
604 core2_ratio = (div >> 28) & 0x7; in exynos4x12_get_arm_clk()
624 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ in exynos5_get_arm_clk()
625 arm_ratio = (div >> 0) & 0x7; in exynos5_get_arm_clk()
626 arm2_ratio = (div >> 28) & 0x7; in exynos5_get_arm_clk()
643 if (s5p_get_cpu_rev() == 0) { in exynos4_get_pwm_clk()
649 sel = (sel >> 24) & 0xf; in exynos4_get_pwm_clk()
651 if (sel == 0x6) in exynos4_get_pwm_clk()
653 else if (sel == 0x7) in exynos4_get_pwm_clk()
655 else if (sel == 0x8) in exynos4_get_pwm_clk()
658 return 0; in exynos4_get_pwm_clk()
662 * PWM_RATIO [3:0] in exynos4_get_pwm_clk()
665 ratio = ratio & 0xf; in exynos4_get_pwm_clk()
670 return 0; in exynos4_get_pwm_clk()
702 * UART0_SEL [3:0] in exynos4_get_uart_clk()
710 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
712 if (sel == 0x6) in exynos4_get_uart_clk()
714 else if (sel == 0x7) in exynos4_get_uart_clk()
716 else if (sel == 0x8) in exynos4_get_uart_clk()
719 return 0; in exynos4_get_uart_clk()
723 * UART0_RATIO [3:0] in exynos4_get_uart_clk()
731 ratio = (ratio >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
749 * UART0_SEL [3:0] in exynos4x12_get_uart_clk()
756 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4x12_get_uart_clk()
758 if (sel == 0x6) in exynos4x12_get_uart_clk()
760 else if (sel == 0x7) in exynos4x12_get_uart_clk()
762 else if (sel == 0x8) in exynos4x12_get_uart_clk()
765 return 0; in exynos4x12_get_uart_clk()
769 * UART0_RATIO [3:0] in exynos4x12_get_uart_clk()
776 ratio = (ratio >> (dev_index << 2)) & 0xf; in exynos4x12_get_uart_clk()
789 int shift = 0; in exynos4_get_mmc_clk()
792 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_mmc_clk()
794 if (sel == 0x6) in exynos4_get_mmc_clk()
796 else if (sel == 0x7) in exynos4_get_mmc_clk()
798 else if (sel == 0x8) in exynos4_get_mmc_clk()
801 return 0; in exynos4_get_mmc_clk()
804 case 0: in exynos4_get_mmc_clk()
819 return 0; in exynos4_get_mmc_clk()
825 ratio = (ratio >> shift) & 0xf; in exynos4_get_mmc_clk()
826 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; in exynos4_get_mmc_clk()
845 * MMC4_RATIO [3:0] in exynos4_set_mmc_clk()
887 clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), in exynos5_set_mmc_clk()
888 (div & 0xff) << ((dev_index << 4) + 8)); in exynos5_set_mmc_clk()
901 * MMC0_RATIO [9:0] in exynos5420_set_mmc_clk()
908 clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); in exynos5420_set_mmc_clk()
922 * FIMD0_SEL [3:0] in exynos4_get_lcd_clk()
925 sel = sel & 0xf; in exynos4_get_lcd_clk()
928 * 0x6: SCLK_MPLL in exynos4_get_lcd_clk()
929 * 0x7: SCLK_EPLL in exynos4_get_lcd_clk()
930 * 0x8: SCLK_VPLL in exynos4_get_lcd_clk()
932 if (sel == 0x6) in exynos4_get_lcd_clk()
934 else if (sel == 0x7) in exynos4_get_lcd_clk()
936 else if (sel == 0x8) in exynos4_get_lcd_clk()
939 return 0; in exynos4_get_lcd_clk()
943 * FIMD0_RATIO [3:0] in exynos4_get_lcd_clk()
946 ratio = ratio & 0xf; in exynos4_get_lcd_clk()
964 * FIMD0_SEL [3:0] in exynos5_get_lcd_clk()
967 sel = sel & 0xf; in exynos5_get_lcd_clk()
970 * 0x6: SCLK_MPLL in exynos5_get_lcd_clk()
971 * 0x7: SCLK_EPLL in exynos5_get_lcd_clk()
972 * 0x8: SCLK_VPLL in exynos5_get_lcd_clk()
974 if (sel == 0x6) in exynos5_get_lcd_clk()
976 else if (sel == 0x7) in exynos5_get_lcd_clk()
978 else if (sel == 0x8) in exynos5_get_lcd_clk()
981 return 0; in exynos5_get_lcd_clk()
985 * FIMD0_RATIO [3:0] in exynos5_get_lcd_clk()
988 ratio = ratio & 0xf; in exynos5_get_lcd_clk()
1006 * 0: SCLK_RPLL in exynos5420_get_lcd_clk()
1019 * FIMD1_RATIO [3:0] in exynos5420_get_lcd_clk()
1022 ratio = ratio & 0xf; in exynos5420_get_lcd_clk()
1041 sel = (readl(&clk->src_disp10) >> 4) & 0x7; in exynos5800_get_lcd_clk()
1049 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()
1056 * FIMD1_RATIO [3:0] in exynos5800_get_lcd_clk()
1058 ratio = readl(&clk->div_disp10) & 0xf; in exynos5800_get_lcd_clk()
1070 * CLK_CAM [0] in exynos4_set_lcd_clk()
1082 * FIMD0_SEL [3:0] in exynos4_set_lcd_clk()
1086 * set lcd0 src clock 0x6: SCLK_MPLL in exynos4_set_lcd_clk()
1088 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); in exynos4_set_lcd_clk()
1092 * CLK_FIMD0 [0] in exynos4_set_lcd_clk()
1100 setbits_le32(&clk->gate_ip_lcd0, 1 << 0); in exynos4_set_lcd_clk()
1104 * FIMD0_RATIO [3:0] in exynos4_set_lcd_clk()
1112 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); in exynos4_set_lcd_clk()
1122 * CLK_CAM [0] in exynos5_set_lcd_clk()
1134 * FIMD0_SEL [3:0] in exynos5_set_lcd_clk()
1138 * set lcd0 src clock 0x6: SCLK_MPLL in exynos5_set_lcd_clk()
1140 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); in exynos5_set_lcd_clk()
1144 * CLK_FIMD0 [0] in exynos5_set_lcd_clk()
1152 setbits_le32(&clk->gate_ip_disp1, 1 << 0); in exynos5_set_lcd_clk()
1156 * FIMD0_RATIO [3:0] in exynos5_set_lcd_clk()
1164 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); in exynos5_set_lcd_clk()
1176 * 0: SCLK_RPLL in exynos5420_set_lcd_clk()
1180 cfg &= ~(0x1 << 4); in exynos5420_set_lcd_clk()
1181 cfg |= (0 << 4); in exynos5420_set_lcd_clk()
1186 * FIMD1_RATIO [3:0] in exynos5420_set_lcd_clk()
1189 cfg &= ~(0xf << 0); in exynos5420_set_lcd_clk()
1190 cfg |= (0 << 0); in exynos5420_set_lcd_clk()
1206 cfg = readl(&clk->src_disp10) | (0x7 << 4); in exynos5800_set_lcd_clk()
1211 * FIMD1_RATIO [3:0] in exynos5800_set_lcd_clk()
1213 clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); in exynos5800_set_lcd_clk()
1223 * FIMD0_SEL [3:0] in exynos4_set_mipi_clk()
1227 * set mipi0 src clock 0x6: SCLK_MPLL in exynos4_set_mipi_clk()
1229 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); in exynos4_set_mipi_clk()
1233 * FIMD0_MASK [0] in exynos4_set_mipi_clk()
1237 * set src mask mipi0 0x1: Unmask in exynos4_set_mipi_clk()
1239 setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); in exynos4_set_mipi_clk()
1243 * CLK_FIMD0 [0] in exynos4_set_mipi_clk()
1255 * FIMD0_RATIO [3:0] in exynos4_set_mipi_clk()
1263 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); in exynos4_set_mipi_clk()
1282 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) { in exynos5_set_epll_clk()
1290 epll_con_k = exynos5_epll_div[i].k_dsm << 0; in exynos5_set_epll_clk()
1308 start = get_timer(0); in exynos5_set_epll_clk()
1311 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { in exynos5_set_epll_clk()
1317 return 0; in exynos5_set_epll_clk()
1328 setbits_le32(EXYNOS5_AUDIOSS_BASE, 1 << 0); in exynos5420_set_i2s_clk_source()
1330 return 0; in exynos5420_set_i2s_clk_source()
1339 if (i2s_id == 0) { in exynos5_set_i2s_clk_source()
1350 return 0; in exynos5_set_i2s_clk_source()
1361 if ((dst_frq == 0) || (src_frq == 0)) { in exynos5_set_i2s_clk_prescaler()
1368 if (i2s_id == 0) { in exynos5_set_i2s_clk_prescaler()
1389 return 0; in exynos5_set_i2s_clk_prescaler()
1398 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1399 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1425 if (input_rate == 0 || target_rate == 0) in clock_calc_best_scalar()
1441 if (error >= 0 && error <= best_error) { in clock_calc_best_scalar()
1459 unsigned mask = 0xff; in exynos5_set_spi_clk()
1463 if (main < 0) { in exynos5_set_spi_clk()
1474 shift = 0; in exynos5_set_spi_clk()
1484 shift = 0; in exynos5_set_spi_clk()
1489 shift = 0; in exynos5_set_spi_clk()
1505 return 0; in exynos5_set_spi_clk()
1516 unsigned div_mask = 0xf, pre_div_mask = 0xff; in exynos5420_set_spi_clk()
1521 if (main < 0) { in exynos5420_set_spi_clk()
1552 pre_shift = 0; in exynos5420_set_spi_clk()
1570 return 0; in exynos5420_set_spi_clk()
1583 ratio &= 0xf; in exynos4_get_i2c_clk()
1600 return 0; in get_pll_clk()
1613 return 0; in get_arm_clk()
1623 return 0; in get_i2c_clk()
1636 return 0; in get_pwm_clk()
1644 case 0: in get_uart_clk()
1669 return 0; in get_uart_clk()
1680 case 0: in get_mmc_clk()
1703 if (div > 0) in set_mmc_clk()
1729 return 0; in get_lcd_clk()
1760 return 0; in set_spi_clk()
1769 return 0; in set_i2s_clk_prescaler()
1781 return 0; in set_i2s_clk_source()
1789 return 0; in set_epll_clk()